A curable composition for imprinting satisfies the following A to C: A: the curable composition includes a polyfunctional polymerizable compound having a polymerizable group equivalent of 150 or higher; B: the curable composition includes a photopolymerization initiator; and C: the curable composition satisfies at least one of a condition that the content of an ultraviolet absorber in which the light absorption coefficient at a maximum emission wavelength of an irradiation light source is 1/2 or higher of the light absorption coefficient of the photopolymerization initiator is 0.5 to 8 mass % with respect to non-volatile components or a condition that the content of a polymerization inhibitor is 0.1 to 5 mass % with respect to the non-volatile components. The non-volatile components refer to components in the curable composition for imprinting other than a solvent.

The printed circuit board according to the embodiment includes a first insulating layer; a first circuit pattern disposed on a lower surface of the first insulating layer or inside the first insulating layer; a second circuit pattern disposed on an upper surface of the first insulating layer; and a second insulating layer disposed on the upper surface of the first insulating layer and to surround the second circuit pattern; wherein the second circuit pattern is an outermost circuit pattern, wherein the second circuit pattern and the second insulating layer are disposed to protrude on the upper surface of the first insulating layer, and wherein a height of the second circuit pattern is greater than a height of the second insulating layer.

A circuit board is manufactured by mounting a first circuit layer, mounting a conductive bump on the first circuit layer, covering the first circuit layer with a first dielectric layer which exposes the conductive bump, mounting a second dielectric layer on the first dielectric layer with a second dielectric layer opening that exposes the conductive bump, and finally, mounting a second circuit layer on the surface of the second dielectric layer and in the second dielectric layer opening. Since the surface roughness of the second dielectric layer and the second dielectric layer opening is low, it is unlikely to form nano voids between the second dielectric layer and the second circuit layer, and the second circuit layer may be attached to the second dielectric layer firmly, which is an advantage for fine line circuit disposal.

A wiring substrate includes a core substrate, and a build-up part formed on the core substrate and including insulating layers and conductor layers. The conductor layers include one or more conductor layers each having a first wiring and a second wiring such that the second wiring has a conductor thickness smaller than a conductor thickness of the first wiring and that a minimum value of a line width of a wiring pattern of the second wiring is smaller than a minimum value of a line width of a wiring pattern of the first wiring.

A package that includes a substrate and an electrical component coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, and a solder resist layer located over a surface of the at least one dielectric layer. The solder resist layer includes a first solder resist layer portion comprising a first thickness, and a second solder resist layer portion comprising a second thickness that is less than the first thickness. The electrical component is located over the second solder resist layer portion.

A circuit board structure, including a circuit layer, a first dielectric layer, a first graphene layer, a first conductive via, and a first built-up circuit layer, is provided. The circuit layer includes multiple pads. The first dielectric layer is disposed on the circuit layer and has a first opening. The first opening exposes the pads. The first graphene layer is conformally disposed on the first dielectric layer and in the first opening, and has a first conductive seed layer region and a first non-conductive seed layer region. The first conductive via is disposed in the first opening. The first built-up circuit layer is disposed corresponding to the first conductive seed layer region. The first built-up circuit layer exposes the first non-conductive seed layer region and is electrically connected to the pads through the first conductive via and the first conductive seed layer region.

An apparatus is provided which comprises: a woven fiber layer, a first resin layer on a first surface of the woven fiber layer, a second resin layer on a second surface of the woven fiber layer, the second surface opposite the first surface, and the first and the second resin layers comprising cured resin, a third resin layer on the first resin layer, and a fourth resin layer on the second resin layer, the third and the fourth resin layers comprising an uncured resin, and wherein the fourth resin layer has a thickness greater than a thickness of the third resin layer. Other embodiments are also disclosed and claimed.

A circuit assembly may include a substrate and a pattern of contact points formed from deformable conductive material supported by the substrate. The assembly may further include an electric component supported by the substrate and having terminals arranged in a pattern corresponding to the pattern of contacts points. The one or more of the terminals of the electric component may contact one or more of the corresponding contact points to form one or more electrical connections between the electric component and the contact points.

A method for producing a wired circuit board, the method including the steps of: a first step of providing an insulating layer having an opening penetrating in the thickness direction at one side surface in the thickness direction of the metal plate, a second step of providing a first barrier layer at one side surface in the thickness direction of the metal plate exposed from the opening by plating, a third step of providing a second barrier layer continuously at one side in the thickness direction of the first barrier layer and an inner surface of the insulating layer facing the opening, a fourth step of providing a conductor layer so as to contact the second barrier layer, and a fifth step of removing the metal plate by etching.

Processes of making an electrical jumper (120) for electrical devices are provided. A micro-replication stamp (300) is used to press a layer of curable material (124) on a circuit substrate (102) to make patterned features. A conductive liquid (230) is disposed into the patterned features to make electrically conductive traces (126) that pass over a circuitry (110) and connect electrical contacts (122A, 122B). In some cases, the stamp (300) has a standoff (310).