A method for manufacturing a printed wiring board includes forming the outermost conductor layer on the outermost resin insulating layer, forming a solder resist layer on the outermost resin insulating layer such that the solder resist layer covers the outermost conductor layer formed on the outermost resin insulating layer, irradiating plasma upon an exposed surface of the solder resist layer formed on the outermost conductor layer, forming a catalyst on the exposed surface of the solder resist layer formed on the outermost conductor layer, and forming an electroless plating layer on the exposed surface of the solder resist layer via the catalyst formed on the exposed surface of the solder resist layer such that the electroless plating layer has a film thickness in a range of 0.22 μm to 0.38 μm.

A wiring substrate includes an insulating layer, a stack including wiring layers and photosensitive-resin insulating layers on a first surface of the insulating layer, a wiring layer on a second surface of the insulating layer, having a lower wiring density than the wiring layers, a metal core plate buried in the insulating layer and positioned on the stack side with respect to the center of the insulating layer in its thickness direction, and a via wiring buried in the insulating layer to have a first end face exposed at the first surface and joined to the lowermost one of the wiring layers, and a second end face joined to the metal core plate. The first surface and the first end face are substantially flush with each other. The wiring layers include a signal line, and a ground line concentrically formed around the signal line, with a predetermined interval therebetween.

A process for the large-scale manufacturing vertically standing hybrid nanometer scale structures of different geometries including fractal architecture of nanostructure within a nano/micro structures made of flexible materials, on a flexible substrate including textiles is disclosed. The structures increase the surface area of the substrate. The structures maybe coated with materials that are sensitive to various physical parameters or chemicals such as but not limited to humidity, pressure, atmospheric pressure, and electromagnetic signals originating from biological or non-biological sources, volatile gases and pH. The increased surface area achieved through the disclosed process is intended to improve the sensitivity of the sensors formed by coating of the structure and substrate with a material which can be used to sense physical parameters and chemicals as listed previously. An embodiment with the structures on a textile substrate coated with a conductive, malleable and bio-compatible sensing material for use as a biopotential measurement electrode is provided.

A printed circuit board and an electronic component-embedded substrate including the same are provided. The printed circuit board includes a first insulating layer, a second insulating layer disposed on the first insulating layer, a barrier layer disposed between the first and second insulating layers, a cavity penetrating through one of the first and second insulating layers, and a first wiring layer at least partially in contact with the barrier layer. The barrier layer has a modulus lower than a modulus of each of the first and second insulating layers.

A method for manufacturing a circuit board comprises steps of providing a single-sided board comprising a first insulating base, a copper layer, and at least one first conductive structure; providing a laminated board comprising a metal layer, a third insulating base, a metal shielding layer, and a second insulating base; forming a wiring layer by the metal layer comprising at least one signal wire and at least one connecting pad; defining at least one second through hole each passing through the second insulating base, the metal shielding layer, and the third insulating base; forming a second conductive structure in each second through hole; providing a double-sided board comprising a wiring layer, a fourth insulating base, a first copper foil; and at least one third conductive structure; pressing the single-sided board, at least one middle structure, and the double-sided board in that sequence to form the circuit board.

An embodiment includes an apparatus comprising: a rod-shaped substrate including a rod long axis; a first layer, including a first interconnect, substantially surrounding the substrate in a first plane that is orthogonal to the rod long axis; and a second layer, including a second interconnect, substantially surrounding the first layer in the first plane. Other embodiments are described herein.

A wiring substrate includes a core substrate, and a build-up layer including conductor layers and insulating layers alternately laminated on the substrate and via conductors formed in the insulating layers, each insulating layer having a coating layer and a support layer stacked on the coating layer such that the support layer has surface on which a conductor layer is laminated and the coating layer is covering a conductor layer, each via conductor connecting two conductor layers through an insulating layer. The coating layer has a thickness greater than that of the support layer and includes inorganic filler at content rate of 65 to 85% by mass, and the support layer includes inorganic filler at different content rate such that thermal expansion coefficient of the coating layer is smaller than that of the support layer and the coefficients of the coating and support layers have difference of 30 ppm/° C. or less.

A manufacturing method of a circuit substrate includes the following steps. A core layer having a core dielectric layer, a first patterned circuit layer and a second patterned circuit layer is provided. An electroless plating nickel layer is formed on the first patterned circuit layer and the second patterned circuit layer. The electroless plating nickel layer has a first thickness, and the first thickness is between 1 micrometer and 10 micrometers. A reducing process is performed on the electroless plating nickel layer so that the electroless plating nickel layer is thinned from the first thickness to a second thickness to form a thinned electroless plating nickel layer. The second thickness is between 0.01 micrometers and 0.9 micrometers. An electroless plating palladium layer is formed on the thinned electroless plating nickel layer. A surface metal passivation layer is formed on the electroless plating palladium layer.

An integrated circuit package and manufacturing method thereof are described. The integrated circuit package includes pin up conductive plating to form an interconnect, where an opening on a patterned fifth layer photo-resist material located at bottom portion of a base developed for etching selectively the base to form at least an internal opening and at least a positioning opening, wherein the internal opening corresponds with an inside area of a first patterned conductive layer, and the positioning opening corresponds with an outside area of the first patterned conductive layer.

A second wiring layer is connected to a first wiring layer via an insulating layer. The second wiring layer comprises pad structures. Each pad structure includes a first metal layer formed on the insulating layer, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The pad structures comprises a first pad structure and a second pad structure. A via-wiring diameter of the first pad structure is different from a via-wiring diameter of the second pad structure. A distance from an upper surface of the insulating layer to an upper surface of the second metal layer of the first pad structure is the same as a distance from the upper surface of the insulating layer to an upper surface of the second metal layer of the second pad structure.