A method of mounting a plurality of semiconductor or microelectronic chips or dies, the method including providing a carrier, temporarily adhering the plurality of semiconductor or microelectronic chips or dies to the carrier with active faces of the chips or dies facing towards the carrier, covering backsides of the chips and filling empty spaces between the chips or dies with a metallic material to thereby define an assembly of the chips or dies and the metallic material, and releasing the assembly from the carrier, wherein each chip or die comprises at least one bonding ring higher than a height of the active face of the respective chip or die or any connections on the active face of the respective chip or die.

A method of mounting a plurality of semiconductor or microelectronic chips or dies, the method including providing a carrier, temporarily adhering the plurality of semiconductor or microelectronic chips or dies to the carrier with active faces of the chips or dies facing towards the carrier, covering backsides of the chips and filling empty spaces between the chips or dies with a metallic material to thereby define an assembly of the chips or dies and the metallic material, and releasing the assembly from the carrier, wherein each chip or die comprises at least one bonding ring higher than a height of the active face of the respective chip or die or any connections on the active face of the respective chip or die.

A manufacturing apparatus that includes a conveyance device that moves a stage, where an electronic device shaped by multiple layers is placed, in X-axis and Y-axis directions. A first shaping unit, a second shaping unit, and a component mounting unit are arranged within a range in which the stage can move. The manufacturing apparatus performs additive manufacturing of the electronic device on the stage by performing a sequential movement of the stage to respective working positions of different units. As a result, in this manufacturing apparatus, a workpiece on the stage does not have to be removed and repositioned during each work process such as shaping by a first shaping unit, shaping by a second shaping unit, and electronic component mounting by a component mounting unit.

A method for manufacturing a circuit board with narrow conductive traces and narrow spaces between traces includes a base layer and two first wiring layers disposed on opposite surfaces of the base layer. Each first wiring layer includes a first bottom wiring and a first electroplated copper wiring. The first bottom wiring is formed on the base layer. The first bottom wiring includes a first end facing the base layer, a second end opposite to the first end, and a first sidewall connecting the first end and the second end. The first electroplated copper wiring covers the second end and the first sidewall of the first bottom wiring.

Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.

A three-dimensional electronic, biological, chemical, thermal management, or electromechanical apparatus and method thereof. One or more layers of a three-dimensional structure are deposited on a substrate. The three-dimensional structure is configured to include one or more internal cavities using, an extrusion-based additive manufacturing system enhanced with a range of secondary embedding processes. The three-dimensional structure includes one or more structural integrated metal objects spanning the one or more of the internal cavities of the three-dimensional structure for enhanced electromagnetic properties and bonded between two or more other metal objects located at the same layer or different layers of the three-dimensional structure.

An ink layer of an electrically conductive ink is formed on a sheet-like base and then the base is bent-deformed before the ink layer is cured, followed by curing the ink layer, thereby forming wiring. The ink layer is pliable during the bending deformation of the base, preventing breakage of the ink layer associated with the bending deformation of the base, and preventing damage to the wiring even when the wiring is finely formed.

In multilayer circuit substrate wiring patterns and reference marks are formed on an upper surface of each insulating layer in a predetermined positional relationship, and the reference marks on the insulating layers are formed at overlapping positions when viewed from above. Furthermore, the reference mark on each layer is formed by changing a size or a shape such that from a specific edge portion recognized when center coordinates of the reference mark is detected by image processing a specific edge portion of the reference mark on a lower layer of the specific edge portion does not protrude considering a positional deviation at the time of manufacturing. The multiple insulating layers are formed of an insulating material having light transparency or an insulating material designed to be extremely thin so that a lower layer can be seen through even if the light transparency is poor.

A semiconductor device has a plurality of interconnected modular units to form a 3D semiconductor package. Each modular unit is implemented as a vertical component or a horizontal component. The modular units are interconnected through a vertical conduction path and lateral conduction path within the vertical component or horizontal component. The vertical component and horizontal component each have an interconnect interposer or semiconductor die. A first conductive via is formed vertically through the interconnect interposer. A second conductive via is formed laterally through the interconnect interposer. The interconnect interposer can be programmable. A plurality of protrusions and recesses are formed on the vertical component or horizontal component, and a plurality of recesses on the vertical component or horizontal component. The protrusions are inserted into the recesses to interlock the vertical component and horizontal component. The 3D semiconductor package can be formed with multiple tiers of vertical components and horizontal components.

A semiconductor device has a plurality of interconnected modular units to form a 3D semiconductor package. Each modular unit is implemented as a vertical component or a horizontal component. The modular units are interconnected through a vertical conduction path and lateral conduction path within the vertical component or horizontal component. The vertical component and horizontal component each have an interconnect interposer or semiconductor die. A first conductive via is formed vertically through the interconnect interposer. A second conductive via is formed laterally through the interconnect interposer. The interconnect interposer can be programmable. A plurality of protrusions and recesses are formed on the vertical component or horizontal component, and a plurality of recesses on the vertical component or horizontal component. The protrusions are inserted into the recesses to interlock the vertical component and horizontal component. The 3D semiconductor package can be formed with multiple tiers of vertical components and horizontal components.