A resilient electrical connector assembly includes a base PCB and stacked layers of interconnected resilient conductive structures where each structure has at least two resilient conductive strips and at least two conductive contacts. One contact is integrated with a conductive path on the base PCB and another contact pad is positioned to establish a conductive path with a target PCB when the latter is mounted parallel to the base PCB. The resilient conductive strips flex due to a compressive force exerted between the base PCB and target PCB on the stacked layers. The resilient conductive structures are formed by depositing metal to sequentially form each of the stacked layers with one contact being initially formed in engagement with the conductive path on the base PCB.

A touch panel has an active area and a non-active area disposed at an outer side of the active area defined therein. The touch panel includes a support member and a conductive layer formed on the support member and including an electrode part in the active area to sense touch and a wiring part disposed in the non-active area to be connected to the electrode part. In the non-active area, the wiring part is disposed on the support member and the electrode part is partially disposed on the wiring part.

[Object] Provided are a laminate film and an electrode substrate film with excellent etching quality, in which a circuit pattern formed by etching processing is less visible under highly bright illumination, and a method of manufacturing the same.

[Solving Means] A laminate film includes a transparent substrate 60 formed of a resin film and a layered film provided on at least one surface of the transparent substrate. The layered film includes metal absorption layers 61 and 63 as a first layer and metal layers (62, 65), (64, 66) as a second layer, counted from the transparent substrate side. The metal absorption layers are formed by a reactive sputtering method which uses a metal target made of Ni alone or an alloy containing two or more elements selected from Ni, Ti, Al, V, W, Ta, Si, Cr, Ag, Mo, and Cu, and a reactive gas containing oxygen. The reactive gas contains hydrogen.

[Object] Provided are an electrode substrate film in which a circuit pattern formed of a metal thin line is less visible even under highly bright illumination, and a laminate film applied to the same.

[Solving Means] An electrode substrate film with a transparent substrate 52 and a metal laminate thin line includes a metal absorption layer 51 with a film thickness of 20 nm to 30 nm inclusive as a first layer, and a metal layer 50 as a second layer, counted from the transparent substrate side, the laminate thin line having a line width of 20 μm or less. Optical constants of the metal absorption layer in a visible wavelength range (400 to 780 nm) satisfy conditions that a refractive index is 2.0 to 2.2 and an extinction coefficient is 1.8 to 2.1 at a wavelength of 400 nm, the refractive index is 2.4 to 2.7 and the extinction coefficient is 1.9 to 2.3 at a wavelength of 500 nm, the refractive index is 2.8 to 3.2 and the extinction coefficient is 1.9 to 2.5 at a wavelength of 600 nm, the refractive index is 3.2 to 3.6 and the extinction coefficient is 1.7 to 2.5 at a wavelength of 700 nm, and the refractive index is 3.5 to 3.8 and the extinction coefficient is 1.5 to 2.4 at a wavelength of 780 nm. An average reflectance in the visible wavelength range attributed to reflection at an interface between the transparent substrate and the metal absorption layer is 20% or less, and a difference between a highest reflectance and a lowest reflectance in the visible wavelength range is 10% or less.

Surface mount components and related methods involve thin film circuits between first and second insulating substrates. The thin film circuits may include passive components, including resistors, capacitors, inductors, arrays of such components, networks, or filters of multiple passive components. Such thin film circuit(s) can be sandwiched between first and second insulating substrates with internal conductive pads which are exposed to the outside of the surface mount component and electrically connected to external terminations. External terminations may include at least one layer of conductive polymer. Optional shield layers may protect the surface mount components from signal interference. A cover substrate may be formed with a plurality of conductive elements that are designed to generally align with the conductive pads such that conductive element portions are exposed in groups along surfaces of a device.

A method of manufacturing a semiconductor device includes providing a first semiconductor chip comprising a first metallic structure, a first surface and a second surface opposite to the first surface; providing a second semiconductor chip comprising a second metallic structure; bonding the first semiconductor chip with the second semiconductor chip on the second surface; forming a first recessed portion including a first sidewall and a first bottom surface coplanar with a top surface of the first metallic structure; forming a second recessed portion including a second sidewall and a second bottom surface coplanar with a top surface of the second metallic structure; forming a dielectric layer over the first sidewall and the second sidewall; and forming a conductive material over the dielectric layer, the top surface of the first metallic structure and the top surface of the second metallic structure.

A method of manufacturing a semiconductor device includes providing a first semiconductor chip comprising a first metallic structure, a first surface and a second surface opposite to the first surface; providing a second semiconductor chip comprising a second metallic structure; bonding the first semiconductor chip with the second semiconductor chip on the second surface; forming a first recessed portion including a first sidewall and a first bottom surface coplanar with a top surface of the first metallic structure; forming a second recessed portion including a second sidewall and a second bottom surface coplanar with a top surface of the second metallic structure; forming a dielectric layer over the first sidewall and the second sidewall; and forming a conductive material over the dielectric layer, the top surface of the first metallic structure and the top surface of the second metallic structure.

A printed circuit board has a double-sided substrate with an insulation layer, a bonding member, a base layer of an aluminum material, and a circuit pattern; a second insulation layer; a second bonding member; a second base layer; a through hole; a zinc substitution layer; a plating layer; and a second circuit pattern.

A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a component embedded in the stack, and a functional film covering at least part of the component and having an inhomogeneous thickness distribution over at least part of a surface of the component.

The present disclosure provides a method for producing a wiring substrate. A seeded substrate including an insulation substrate, a conductive undercoat layer, and a conductive seed layer provided in a first region, in that order, is first prepared. An insulation layer covering the seed layer and the undercoat layer is then formed. Subsequently, the insulation layer is etched to expose a surface of the seed layer and form a remaining insulation layer covering the undercoat layer in the second region. Subsequently, a voltage is applied between an anode and the seed layer while a solid electrolyte membrane containing a metal ion-containing aqueous solution disposed between the seed layer and the anode and the membrane and the seed layer pressed into contact with each other, thereby a metal layer being formed on the surface of the seed layer. Thereafter, the remaining insulation layer is removed and the undercoat layer is etched.