A chip package is provided. The chip package includes a semiconductor chip and a semiconductor die over the semiconductor chip. The chip package also includes a dielectric layer over the semiconductor chip and encapsulating the semiconductor die, and the dielectric layer is substantially made of a semiconductor oxide material. The chip package further includes a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting a conductive pad of the semiconductor chip.

An extremely thin copper foil with a carrier is provided that can keep stable releasability even after being heated for a prolonged time at a high temperature of 350 C. or more. The extremely thin copper foil with a carrier includes a carrier composed of a glass or ceramic material; an intermediate layer provided on the carrier and composed of at least one metal selected from the group consisting of Cu, Ti, Al, Nb, Zr, Cr, W, Ta, Co, Ag, Ni, In, Sn, Zn, Ga, and Mo; a release layer provided on the intermediate layer and including a carbon sublayer and a metal oxide sublayer or containing metal oxide and carbon; and an extremely thin copper layer provided on the release layer.

The disclosure provides a three-dimensional circuit assembly including a printed circuit board comprising a top film surface and a bottom film surface opposite to the top film surface. The three-dimensional circuit assembly may also include a first layer of a composite material bonded or laminated on the top film surface. The three-dimensional circuit assembly may further include a second layer of the composite material bonded or laminated on the bottom film surface of the printed circuit board.

An electrically conducting substrate includes a plurality of layers. A strain gauge is deposited on a layer of the plurality of layers. The strain gauge measures the stress and/or strain of the electrically conducting substrate. This allows the strain gauge to determine whether a stress or strain of the electrically conducting substrate has caused the electrically conducting substrate to deform, crack, or break.

A wiring circuit board includes a metal supporting board, first and second metal thin films, an insulating layer, and a conductive layer, where the resistance between the conductive layer and metal supporting board are lowered. The first metal thin film is disposed on one surface of the metal supporting board in the thickness direction, with the insulating layer having a through hole. The second metal thin film is disposed on one surface of the insulating layer in the thickness direction with the conductive layer disposed thereon. In the through hole, the first and second metal thin films, whose surfaces contact, are disposed between the metal supporting board and the conductive layer, and the other surface of the first metal thin film is in contact with the one surface of the metal supporting board. The other surface of the second metal thin film is in contact with the conductive layer.

A method of manufacturing a printed circuit board includes providing an insulating layer, forming a plating seed layer on the insulating layer, forming a first circuit pattern on the plating seed layer and a second circuit pattern on the first circuit pattern, and forming a top metal layer on the second circuit pattern. The second circuit pattern can be thinner than the first circuit pattern, and the top metal layer can be wider than the second circuit pattern.

Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.

Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.

A light emitting diode (LED) module may include a direct current (DC) voltage node formed on a first layer. The DC voltage node may be configured to sink a first current. One or more devices may be formed on the first layer configured to provide a second current to one or more LEDs. A device of the one or more devices may carry a steep slope voltage waveform. A local shielding area may be formed in a second layer directly below the DC voltage node and the one or more devices. The local shielding area may include a substantially continuous area of conductive material. A conductive via may extend through one or more layers. The conductive via may electrically connect the DC voltage node and the local shielding area.

Provided is an electronic component package for electromagnetic interference shielding. The electronic component package for electromagnetic interference shielding according to an embodiment of the present invention comprises a substrate where electronic components are mounted, a molding member formed on the substrate and the electronic components, a magnetic layer formed on the molding member, and a conductive layer formed on the magnetic layer. Electromagnetic waves generated from the electronic components embeded in the molding member are absorbed in the magnetic layer to thus prevent or reduce harmful influence on other electronic components mounted in adjacent places. In addition, harmful electromagnetic waves generated from the outside may be shielded due to the conductive layer formed on the magnetic layer, thereby protecting electronic components embeded in the molding member from being influenced by the electromagnetic waves.