A printed circuit board includes a first insulating layer; a first wiring layer having at least a portion buried in one surface side of the first insulating layer and having at least a portion of one surface exposed from the one surface of the first insulating layer; a metal post disposed on the exposed one surface of at least the portion of the first wiring layer; and a second wiring layer disposed on the other surface of the first insulating layer. A width of a first surface, connected to the exposed one surface of at least a portion of the first wiring layer, of the metal post, is greater than a width of a second surface of the metal post opposing the first surface.

A wiring substrate includes a first insulating layer, a conductor layer including first and second pads, a second insulating layer having first openings exposing the first pads and a second opening exposing the second pads, metal posts formed on the first pads and filling the first openings, and a wiring structure positioned in the second opening and having first and second connection pads such that the second connection pads are connected to the second pads. The upper surfaces of the first connection pads and the upper surfaces of the metal posts form a component mounting surface having first, second and third regions, the first connection pads are formed in the first, second and third regions and include a group of first connection pads formed in the first and second regions and electrically connected and a group of first connection pads formed in the first and third regions and electrically connected.

A printed circuit board includes: an insulating layer; a plurality of pads disposed on the insulating layer; and a plurality of insulating walls disposed on the insulating layer, and at least partially covering side surfaces of the plurality of pads, respectively, while being free from surfaces of the plurality of pads, respectively. The plurality of insulating walls are disposed to be spaced apart from each other on the insulating layer.

A wiring substrate includes a first insulating layer, a conductor layer including first and second conductor pads, a second insulating layer having an opening exposing the second conductor pads, and a wiring structure including a resin insulating layer and a wiring layer and formed in the opening of the second insulating layer. The wiring structure has first surface side connection pads, second surface side connection pads and electrically connected to the second conductor pads of the conductor layer, and conductors that electrically connect the first surface side connection pads and the second surface side connection pads, the first surface side connection pads form a component mounting surface having first and second component mounting region, and the first surface side connection pads include a group of pads in the first region and a group of pads in the second region electrically connected to the group of pads in the first region.

A circuit carrier includes a substrate, a first build-up circuit structure, a second build-up circuit structure, a fine redistribution structure and at least one conductive through hole. The substrate has a top surface and a bottom surface opposite to each other. The first build-up circuit structure is disposed on the top surface of the substrate and electrically connected to the substrate. The second build-up circuit structure is disposed on the bottom surface of the substrate and electrically connected to the substrate. The fine redistribution structure is directly attached on the first build-up circuit structure, wherein a line width and a line spacing of the fine redistribution structure are smaller than those of the first build-up circuit structure. The conductive through hole penetrates the fine redistribution structure and a portion of the first build-up circuit structure and is electrically connected to the fine redistribution structure and the first build-up circuit structure.

A package structure includes a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a chip, a circuit layer structure, and an insulating protective layer. The composite layer of the non-conductor inorganic material and the organic material is disposed on the metal layer. The sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material. The chip is embedded in the sealant, and the chip has electrode pads. The circuit layer structure is formed on the sealant and the chip. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has conductive blind holes. The insulating protective layer is formed on the circuit layer structure. The insulating protective layer has openings, so as to expose parts of the surface of the circuit layer structure in the openings.

A method for manufacturing a wiring board includes forming on a first support plate a first laminated wiring portion including conductor and insulating layers such that the first portion has a first surface on first support plate side and a second surface, separating the first portion from the first plate, forming a conductor layer exposed on the first surface and including pads, laminating the first portion on a second support plate such that the second surface of the first portion faces second support plate side, forming on the first surface of the first portion a second laminated wiring portion including conductor and insulating layers such that the second portion has a third surface on second support plate side and a fourth surface, forming cavity in the second portion on the second plate such that the cavity exposes the pads, and separating the first and second portions from the second plate.

A printed circuit board includes: a plurality of insulating layers; a plurality of wiring pattern layers disposed on at least one surface of the plurality of insulating layers; a via connecting wiring pattern layers, among the plurality of wiring pattern layers, disposed on upper and lower surfaces of one of the plurality of insulating layers to each other; a connection pad disposed on a surface of an outermost layer among the plurality of insulating layers; and a solder resist having a hole exposing at least a portion of the connection pad. An external surface of the solder resist has surface roughness.

A method of manufacturing a printed circuit board includes forming an intermediate layer on a first conductive layer disposed on a first insulating layer, forming a second conductive layer and a second insulating layer on the intermediate layer, separating the first insulating layer from at least one portion of the first conductive layer, and etching the first conductive layer and the intermediate layer. After the etching, a surface of the second conductive layer protrudes further than a surface of the second insulating layer. The intermediate layer before the etching includes a portion overlapping the second conductive layer in a vertical direction and another portion not overlapping the second conductive layer in the vertical direction.

This disclosure generally relates to high-speed fiber optic networks that use light signals to transmit data over a network. The disclosed subject matter includes devices and methods relating to header subassemblies and/or optoelectronic subassemblies. In some aspects, the disclosed devices and methods may relate to a header subassembly that can include: a multi-layer substrate with a bottom layer, a top layer having top thin film signal lines, and one or more intermediate layers having thick film traces between the top layer and the bottom layer, the thick film traces electrically coupled to the top thin film signal lines; and optoelectronic components positioned over the multi-layer substrate and electrically coupled with the signal lines.