A printed circuit board (PCB) device including one or more insulating layers and one or more conducting layers arranged to form a layer stack; and one or more blind holes disposed along a side edge of the layer stack and parallel to a plane of the layer stack. Each of the one or more blind holes along the side edge of the layer stack is configured to receive a pin. Each pin can make an electrical connection with a corresponding blind hole.

A wiring board includes first insulating layers; first wiring layers; first via wirings; second insulating layers; second wiring layers; second via wirings; and a solder resist layer, wherein the first insulating layers are composed of non-photosensitive resin, wherein the second insulating layers, and the solder resist layer are composed of photosensitive resin, respectively, wherein the first surface of the uppermost first insulating layer and the first end surface of the first via wiring embedded in the uppermost first insulating layer are polished surfaces, wherein the first end surface of the first via wiring embedded in the uppermost first insulating layer is flush with the first surface of the uppermost first insulating layer, and wherein the wiring density of the second wiring layers is higher than the wiring density of the first wiring layers.

Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.

A method of manufacturing a support body includes: (a) preparing a support substrate; (b) preparing a metal foil on which a peeling layer is provided; (c) providing an adhesion adjusting layer on the support substrate in a certain region of the support substrate excluding an outer peripheral portion of the support substrate, wherein the adhesion adjusting layer is configured to adjust a contact area between the peeling layer and the support substrate; and (d) providing the metal foil on the support substrate such that the peeling layer provided on the metal foil faces the support substrate via the adhesion adjusting layer. In step (d), the adhesion adjusting layer is adhered to the support substrate, and the peeling layer is adhered to the outer peripheral portion of the support substrate, and is in contact with the adhesion adjusting layer but is not adhered to the adhesion adjusting layer.

A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.

A temporary carrier according to an embodiment of the present invention may include a core layer, a first Cu foil layer and a second Cu foil layer on surfaces of both sides of the core layer. Each of the first Cu foil layer and the second Cu foil layer may include double Cu foils which are physically attached together.

A temporary carrier according to an embodiment of the present invention may include a core layer, a first Cu foil layer and a second Cu foil layer on surfaces of both sides of the core layer. Each of the first Cu foil layer and the second Cu foil layer may include double Cu foils which are physically attached together.

A component carrier with a double layer structure is illustrated and described. The double layer structure includes an electrically conductive patterned layer structure and a further patterned layer structure made of a two-dimensional material. The patterned layer structure and the further patterned layer structure have at least partly the same pattern. In an embodiment the component carrier includes a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure and at least one double layer structure connected with the stack.

A method includes forming a first redistribution line, forming a polymer layer including a first portion encircling the first redistribution line and a second portion overlapping the first redistribution line, forming a pair of differential transmission lines over and contacting the polymer layer, and molding the pair of differential transmission lines in a molding compound. The molding compound includes a first portion encircling the pair of differential transmission lines, and a second portion overlapping the pair of differential transmission lines. An electrical connector is formed over and electrically coupling to the pair of differential transmission lines.

A printed circuit board includes: an insulating layer; a first circuit pattern embedded in one surface of the insulating layer; and a second circuit pattern disposed on the one surface of the insulating layer and including a first metal layer and a second metal layer disposed on the first metal layer. An average width of the first metal layer is wider than an average width of the second metal layer.