A Data Storage Device (DSD) enclosure includes a chassis and at least one backplane mounted in the chassis. According to one aspect, each backplane includes a row of DSD slots and a switch slot located in a middle portion of the row of DSD slots. A plurality of signal traces connect the DSD slots to the switch slot.

A connecting circuit includes a motherboard, a first back panel, and a second back panel. The motherboard defines a first connector and a second connector. The first connector includes a first address distinguishing pin. The second connector includes a second address distinguishing pin. The first back panel is coupled with the first connector and transmits a first address signal to the first connector. The second back panel is coupled with the second connector and transmits a second address signal to the second connector. The first address distinguishing pin is connected to ground and the second address distinguishing pin is connected to a high level voltage to distinguish the first address signal from the second address signal.

The present invention is a backplane board including a first circuit board, a second circuit board, a first slot in which a first connector is connected with the first circuit board, and a second slot in which a second connector is connected with the second circuit board. The first connector and the second connector are arranged so that pin arrangement of the first connector may be shifted by at least one column in a longitudinal direction against pin arrangement of the second connector.

A configurable mission processor (CMP) is disclosed that includes a chassis with a plurality of reprogrammable processor modules (RPMs) disposed within the chassis. Each RPM has a baseboard with at least one field programmable gate array (FPGA) and a configuration manager configured to accept a configuration file through an externally accessible signal connector, store the configuration file, and selectably program the at least one FPGA using the configuration file. The RPM includes a power submodule that accepts unregulated power through an externally accessible power connector, generates regulated power at a plurality of voltages, and provide the regulated power to the RPM. The RPM may also include an input/output submodule configured to provide a communication channel between the at least one FPGA and external devices through its own externally accessible signal connector. The CMP also includes a backplane that provides only signal and ground interconnections between the baseboards.

An apparatus for distributing current in a low-voltage system includes a plurality of disk-shaped modules that can be arranged adjacent to each other in a row and mounted or locked on a carrier rail. At least one supply module, at least one fuse module, and at least one distributing module are provided. The modules have at least one cross connector for a positive potential and at least one cross connector for a negative potential. The fuse module and the distributing module also have at least one additional cross connector for a potential that is protected by the fuse module.

A connecting circuit includes a motherboard, a first back panel, and a second back panel. The motherboard defines a first connector and a second connector. The first connector includes a first address distinguishing pin. The second connector includes a second address distinguishing pin. The first back panel is coupled with the first connector and transmits a first address signal to the first connector. The second back panel is coupled with the second connector and transmits a second address signal to the second connector. The first address distinguishing pin is connected to ground and the second address distinguishing pin is connected to a high level voltage to distinguish the first address signal from the second address signal.

Disclosed is a method of assembling a backplane connector subassembly for a module of a modular energy system. The backplane connector subassembly physically and electrically connects at least two modules stacked on top of one another. The method includes providing a back panel defining an inner surface, attaching a first support member to the inner surface of the back panel, attaching a second support member to the inner surface of the back panel, attaching the upstream connector to the back panel by sliding a first mating hole defined in the upstream connector onto the first support member, and attaching the downstream connector to the back panel by a sliding a second mating hole defined in the downstream connector onto the second support member. The first support member is configured to support an upstream connector. The second support member is configured to support a downstream connector.

A wall panel system including a first wall panel, the first panel including at least a first panel hook portion. The system also including a second wall panel having a different configuration than the first wall panel. The second panel includes at least a second panel hook portion and a third panel hook portion opposing the second panel hook portion. The first wall panel is configured to engage with the second wall panel to create a wall panel assembly.

A battery charging system including at least two conductors running parallel to one another, an AC/DC converter, the AC/DC converter configured to receive an AC input and to provide a DC output to the at least two conductors and a battery charger, the battery charger (1) including a battery pack receiving portion to receive a removable, rechargeable battery pack and (2) removably, electrically coupled to the at least two conductors to receive the DC output.

A method includes attaching a power electronic substrate to a bottom of a frame. The frame has a box-like rectangular shape with an open top and an open bottom. The method further includes disposing an external conductive terminal on the frame. The external conductive terminal has at least one terminal stub that extends on to the front surface of the power electronic substrate. The method further includes welding the at least one terminal stub to at least one circuit trace disposed on the front surface of the power electronic substrate.