A multilayer substrate includes a multilayer body in which insulating layers are laminated in a laminating direction, a front electrode that is provided on a front surface side of a first insulating layer which is positioned on a front surface side of the multilayer body among the insulating layers, a first internal electrode that is provided on an opposite side to the front electrode with the first insulating layer interposed therebetween, and a first interlayer connection conductor that electrically connects the front electrode and the first internal electrode with each other. The first interlayer connection conductor includes a front side connection surface that is electrically connected with the front electrode and a back side connection surface that is electrically connected with the first internal electrode.

A circuit board with anti-corrosion properties, a method for manufacturing the circuit board, and an electronic device are provided. The circuit board includes a circuit substrate, a first protective layer, and a second protective layer. The circuit substrate includes a base layer and an outer wiring layer formed on the base layer. The circuit substrate further defines a via hole connected to the outer wiring layer. The first protective layer is formed on the outer wiring layer and an inner sidewall of the via hole, and is made of a white oil. The second protective layer is formed on the first protective layer.

A circuit board includes a substrate, a build-up circuit structure, a graphene oxide layer, a graphene layer, and an insulating material layer. The build-up circuit structure is disposed on the substrate, including at least one inner circuit, at least one dielectric layer, an outer circuit, and multiple conductive vias. The dielectric layer is disposed on the inner circuit. The outer circuit is disposed on the dielectric layer. The conductive vias penetrate the dielectric layer and electrically connect the inner circuit and the outer circuit. The graphene oxide layer and the graphene layer are disposed on the build-up circuit structure at an interval. The graphene oxide layer and the graphene layer are respectively disposed in correspondence to the dielectric layer and the outer circuit. The insulating material layer is disposed on the graphene oxide layer and the graphene layer. The insulating material layer has an opening, which exposes the graphene layer.

According to one embodiment, an electronic device includes: a housing; a first electronic component inside the housing; a second electronic component arranged inside the housing and spaced apart from the first electronic component; a female connector electrically connected to the second electronic component, the female connector comprising multiple conductive pins; a male connector electrically connected to the first electronic component and configured to contact at least some of the multiple conductive pins of the female connector, the male connector comprising a base film, a conductive layer formed on one surface of the base film, and an adhesive layer formed on the back surface of the base film, thereby forming a lamination structure; and multiple reinforcement members provided on at least one of one surface of the base film and the back surface thereof so as to form a peripheral portion of the lamination structure.

There is provided a resin composition exhibiting excellent dielectric properties, high adhesion to a low-roughness surface, heat resistance, and excellent water resistance. This resin composition includes (a) a polymer having a polyphenylene ether backbone and a butadiene backbone in one molecule and having at least one selected from the group consisting of a vinyl group, a styryl group, an allyl group, an ethynyl group and a (meth)acryloyl group and at least any one of (b) a polymer including a styrene butadiene backbone and (c) a polymer including a cycloolefin backbone, wherein the content is the component (a) of 15 to 60 parts by weight and the total content of the component (b) and the component (c) is 40 to 85 parts by weight, based on 100 parts by weight of the total content of the component (a), the component (b), and the component (c).

A method of manufacturing a multilayer board includes forming conductor patterns on four or more insulating base material layers, forming a multilayer body by stacking the insulating base material layers in a state in which the conductor patterns face each other with prepreg layers therebetween, and heat-pressing the multilayer body. In a state before the step of heat-pressing, among the prepreg layers, a thickness of an outermost prepreg layer is larger than a thickness of a prepreg layer other than the outermost prepreg layer.

A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure. A component is embedded in the stack. A first thermally conductive block is located above and thermally connected with the component, and a second thermally conductive block is located below and thermally coupled with the component. Heat generated by the component during operation is removed via at least one of the first thermally conductive block and the second thermally conductive block.

A circuit board includes at least one circuit board unit sequentially stacked in a thickness direction of the circuit board, an insulating layer, an electromagnetic shielding layer, and a barrier layer. The circuit board unit includes a substrate layer, and two conductive layers respectively disposed on two opposite sides of the substrate layer in a thickness direction of the substrate layer, and each of the conductive layers includes a plurality of signal lines. The insulating layer is located on a side of an outermost conductive layer away from the substrate layer. The electromagnetic shielding layer is located on a side of the insulating layer away from the substrate layer. The barrier layer is located between the electromagnetic shielding layer and the outermost conductive layer. The barrier layer at least covers a plurality of signal lines in the outermost conductive layer.

Processes for laminating a graphene-coated printed circuit board (PCB) are disclosed. An example laminated PCB may include a lamination stack that may include an inner core, an adhesive layer, and at least one graphene-metal structure. Pressure and heat—which may be applied under vacuum or controlled gas atmosphere—may be applied to the lamination stack, after all materials have been placed. The graphene of the graphene-metal structure is designed to promote high frequency performance and heat management within the PCB.

Embodiments are directed to a method of manufacturing the printed circuit board. The PCB is a multi-layer component, including a dielectric material and an intermediate or second layer adjacently positioned with respect to the dielectric material. The intermediate layer or second layer includes a conductor and fiberglass strands, with the fiberglass strands having an associated orientation. When assembled, the fiberglass and the conductor have a matching orientation and separation distance from a source to a destination.