Patent classifications
H05K2201/029
Thermal management of printed circuit board components
A first thermal management approach involves an air flow through cooling mechanism with multiple airflow channels for dissipating heat generated in a PCA. The air flow direction through at least one of the channels is different from the air flow direction through at least another of the channels. Alternatively or additionally, the airflow inlet of at least one channel is off-axis with respect to the airflow outlet. A second thermal management approach involves the fabrication of a PCB with enhanced durability by mitigating via cracking or PTH fatigue. At least one PCB layer is composed of a base material formed from a 3D woven fiberglass fabric, and conductive material deposited onto the base material surface. A conductive PTH extends through the base material of multiple PCB layers, where the CTE of the base material along the z-axis direction substantially matches the CTE of the conductive material along the x-axis direction.
SURFACE-TREATED GLASS CLOTH, PREPREG, AND PRINTED WIRING BOARD
Provided are a surface-treated glass cloth capable of enhancing insulation reliability when used to prepare a prepreg, a prepreg and a printed wiring board using the surface-treated glass cloth. The surface-treated glass cloth includes a surface treatment layer on a surface, a glass constituting the glass cloth has a composition containing 52.0 to 60.0 mass % of SiO.sub.2, 15.0 to 26.0 mass % of B.sub.2O.sub.3, 9.0 to 18.0 mass % of Al.sub.2O.sub.3, 1.0 to 8.0 mass % of MgO, 1.0 to 10.0 mass % of CaO, 0 to 6.0 mass % of SrO, 0 to 6.0 mass % of TiO.sub.2, and 0.1 to 3.0 mass % in total of F.sub.2 and Cl.sub.2, based on the total amount of the glass, the glass cloth has a surface coverage of 75.0 to 100.0% and a thickness of 8 to 95 μm, and the surface treatment layer contains a silane coupling agent having a methacrylic group and contains no surfactant.
Active ester compound
An active ester compound that can form a cured product having excellent dielectric properties and copper foil adhesion properties is provided, a curable composition including the active ester compound is provided, and a cured product of the curable composition is provided. Also provided are a semiconductor encapsulating material, a printed wiring board, and a build-up film formed by using the curable composition. Specifically, an active ester compound is provided which includes a fluorinated hydrocarbon structural moiety and a plurality of aromatic ester structural moieties in the structure of the molecule and includes an aryloxycarbonyl structure or an arylcarbonyloxy structure at an end of the molecule, a curable composition including the active ester compound, and a cured product of the curable composition, and also provided are a semiconductor encapsulation material, a printed wiring board, and a build-up film formed by using the curable composition.
LAMINATE, PRINTED WIRING BOARD, SEMICONDUCTOR PACKAGE, AND METHOD FOR MANUFACTURING LAMINATE
The present invention relates to a laminate including two or more layers of a composite layer including a fiber substrate and a cured product of a thermosetting resin composition, the two or more layers of the composite layer including one or more layer of a composite layer (X) and one or more layer of a composite layer (Y), the composite layer (X) being a layer including a first fiber substrate constituted by first glass fibers, the composite layer (Y) being a layer including a second fiber substrate constituted by second glass fibers, and the second glass fibers having a higher tensile elastic modulus at 25° C. than the first glass fibers, a printed wiring board including the laminate, a semiconductor package, and a method for producing a laminate.
Bi-layer prepreg for reduced dielectric thickness
An apparatus is provided which comprises: a woven fiber layer, a first resin layer on a first surface of the woven fiber layer, a second resin layer on a second surface of the woven fiber layer, the second surface opposite the first surface, and the first and the second resin layers comprising cured resin, a third resin layer on the first resin layer, and a fourth resin layer on the second resin layer, the third and the fourth resin layers comprising an uncured resin, and wherein the fourth resin layer has a thickness greater than a thickness of the third resin layer. Other embodiments are also disclosed and claimed.
High thermal conductivity prepreg and uses of the same
A high thermal conductivity prepreg is provided. The high thermal conductivity prepreg includes a high thermal conductivity reinforcing material and a dielectric material layer formed on the surface of the high thermal conductivity reinforcing material, wherein the high thermal conductivity reinforcing material is prepared by a process which includes the following steps: (a) providing a precursor aqueous solution, the precursor aqueous solution includes a precursor selected from the group of organic salts, inorganic salts, and combinations thereof; (b) subjecting the precursor aqueous solution to a hydrolysis reaction to form an intermediate product aqueous solution; (c) subjecting the intermediate product aqueous solution to a condensation polymerization reaction to form a pretreatment solution; (d) impregnating a reinforcing material with the pretreatment solution; and (e) oven-drying the impregnated reinforcing material to obtain the high thermal conductivity reinforcing material.
METHOD TO MANUFACTURE CONDUCTIVE ANODIC FILAMENT-RESISTANT MICROVIAS
An electronic printed circuit board structure for mitigating conductive anodic filament growth. The structure includes at least two conductive layers and a dielectric layer sandwiched between the conductive layers. At least one hole extends through the dielectric layer, and a layer of nonconductive material covers the at least one hole, wherein the nonconductive material is glass-free. A conductive plate layer is disposed over the nonconductive material layer to form a via connection in the structure.
CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME
The present disclosure provides a circuit board and a method for manufacturing the circuit board. The circuit board may include: a base board, an embedded component, and an attached component. The base board may define a groove, the embedded component can be disposed in the groove. The attached component can be attached to at least one surface of the base board and connected to the embedded component.
Glass cloth
A glass cloth includes warp yarns and weft yarns formed by bundling in the range of 14 to 55 glass filaments having a diameter in the range of 3.0 to 4.2 μm, and has a weaving density of the warp yarns and the weft yarns of 86 to 140 yarns/25 mm, a thickness of 7.5 to 12.0 μm, a mass of 6.0 to 10.0 g per m.sup.2, and an average number of stages of 2.00 or more and less than 3.00, an average degree of opening, which is indicated as the geometric mean of the degree of opening of the warp yarns and the degree of opening of the weft yarns, in the range of 1.000 to 1.300, and a yarn width ratio, as the ratio of the yarn width of the warp yarns to that of the weft yarns, in the range of 0.720 to 0.960.
Layout routing structure and layout routing method for improving SI performance of signal
A layout routing structure and a layout routing method for improving an SI performance of a signal are provided. Each of two positive and negative differential traces on a PCB includes multiple segments D1, multiple segments D2 and multiple segments D3. In each of the two differential traces, the segment D1 and the segment D2 are staggered and parallel to each other, the segment D2 is routed between any two segments D1, and any two adjacent segments D1 and D2 are connected by the segment D3. In one of the two differential traces, all of the segments D1 are routed on the glass cloth, and all of the segments D2 are routed on the epoxy resin. In the other of the two differential traces, all of the segments D1 are routed on the epoxy resin, and all of the segments D2 are routed on the glass cloth.