A carrier board and a power module using the same are disclosed. The carrier board includes a main body, two metal-wiring layers and at least one metal block. The main body includes at least two terminals and a surface. The two terminals are disposed on the surface. The two metal-wiring layers are disposed on the main body to form two parts of metal traces connected to the two terminals, respectively. The at least one metal block is embedded in the main body and connected to one of the two terminals. A thickness of the two parts of metal traces is less than that of the metal block. The two terminals connected by the two parts of metal traces have a loop inductance less than or equal to 1.4 nH calculated at a frequency greater than 1 MHz.

Embodiments described herein are directed to methods and apparatus for power distribution. The apparatus can include a power distribution network for a plurality of integrated circuits (IC). According to embodiments, the power distribution network includes a plurality of overlapping power/ground (PG) plane segments and one or more non-overlapping PG (no-PG) plane segments. Each overlapping-PG plane segment is separated from another overlapping-PG plane segment by at least one no-PG plane segment. The no-PG plane segments can include at least one of a multilayered power (P) plane segment with no ground reference of any PG plane and a multilayered ground (G) plane segment with no power reference of any PG plane.

A multilayer structure having a main surface includes: a first conductor extending in parallel with the main surface; a second conductor extending in parallel with the main surface and disposed at a different position from the first conductor with respect to a thickness direction of the multilayer structure; and a third conductor having a shape extending in at least any direction as seen in a direction perpendicular to the main surface. In a range higher than a lower end of the third conductor and lower than an upper end of the third conductor in the thickness direction of the multilayer structure, at least a part of the first conductor is included and at least a part of the second conductor is included.

An apparatus includes a substrate, a switching device, a capacitor device, a first via, a second via, a third via and a fourth via. The substrate has a first surface and a second surface and includes a plurality of copper layers including M positive copper layers and N negative copper layers. The M positive copper layers and the N negative copper layers are alternated. The switching device is disposed on the first surface and includes a switching positive terminal and a switching negative terminal. The capacitor device is disposed on the first surface and includes a capacitor positive terminal and a capacitor negative terminal, and the capacitor device forms a capacitor area. The projections of the adjacent positive and negative copper layers and the capacitor area on the first surface at least partially overlap with each other.

The present disclosure relates to light source driving systems, for example laser driving systems. The systems are configured to include a very low inductance current loop for driving an initial part of the current drive signal to turn on the light source. By implementing the system to have a very low inductance current loop, a very fast turn on time may be achieved for the light source, which can be particularly useful for Time of Flight systems that require a very quick turn-on response from the light source.

An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.

An axial field rotary energy device can include rotors having magnets and an axis of rotation. A stator assembly can be located axially between the rotors. The stator assembly can include PCB panels. Each PCB panel can have layers. Each layer can include coils. Each coil can have radial traces relative to the axis. The radial traces can include non-linear radial traces coupled by arch traces that are transverse to the non-linear radial traces.

A capacitor is disposed on a substrate that is insulative. An inductor is disposed on the substrate. The inductor includes a conductor pattern having at least one end connected to the capacitor. The capacitor includes a dielectric film that mainly contains the same constituent element as a constituent element mainly contained in the substrate and at least two electrodes that face each other with the dielectric film interposed therebetween.

A system and method for integrating a magnetic component within a power converter includes a coil integrated on a PCB. The PCB includes multiple layers and traces on each layer to form a single coil or to form multiple coils on the magnetic component. The PCB further includes at least one opening in the PCB through which a core component may pass, such that the magnetic component is defined by the coils and the core material. To reduce eddy currents built up within the traces, the dimensions of traces on a layer are varied and the position of traces between layers of the PCB are varied. The widths and locations of individual traces are selected to reduce coupling of the trace to leakage fluxes within the magnetic component. A floating conductive layer may also be provided to still further reduce the magnitude of eddy currents induced within the coil.

The disclosure relates to an electronic device including a circuit board; a housing; and an antenna, wherein the antenna and the circuit board are fixed inside the housing, wherein the circuit board comprises a first electrostatic protection circuit and a protected circuit, wherein the antenna is electrically connected to a first end of the first electrostatic protection circuit, and electrically connected to a first end of the protected circuit, wherein a second end of the first electrostatic protection circuit is electrically connected to a first ground point, a second end of the protected circuit is electrically connected to a second ground point, and the first electrostatic protection circuit is connected in parallel with the protected circuit, and wherein a trace distance between the second end of the first electrostatic protection circuit and the second end of the protected circuit is less than a first threshold, to reduce parasitic inductance.