The present disclosure relates to optical systems and methods of their manufacture. An example system includes a printed circuit board assembly (PCBA) and an image sensor package coupled to the PCBA by way of a plurality of bond members. The system additionally includes a sensor holder coupled to the PCBA. The image sensor package and the sensor holder are coupled to the PCBA so as to minimize thermally-induced stresses in at least one of: the plurality of bond members, the PCBA, the sensor holder, or the image sensor package.

Electrical insulating properties between adjacent copper plates are improved while a defect of a bonded substrate which is caused by concentration of stress to end portions of the copper plates is prevented. A bonded substrate includes a silicon nitride ceramic substrate, a copper plate, and a bonding layer. The copper plate and the bonding layer are disposed on the silicon nitride ceramic substrate. The bonding layer bonds the copper plate to the silicon nitride ceramic substrate. The bonding layer includes: an interplate portion between the silicon nitride ceramic substrate and the copper plate; and a protruding portion protruding from between the silicon nitride ceramic substrate and the copper plate. Exposure of the silicon nitride ceramic substrate is prevented at a position where the protruding portion is disposed.

A micro-electromechanical system (MEMS) apparatus has an array of micro-mirrors and a control circuit for rotating the micro-mirrors synchronously at a resonant frequency. The MEMS apparatus includes elements with different Coefficients of Thermal Expansion (CTE) for a die substrate coupled to the array of micro-mirrors, a die attach layer, a chip package coupled to the die substrate and a printed circuit board coupled to the chip package. The apparatus provides mechanisms for reducing changes in the resonant frequency due to changes in temperature causing stresses due to a mismatch between the CTE of the different elements. A thermoelectric cooler is used, along with the optional addition of heating resistors, additional pins to distribute stress, and the widened vias allowing room for the pins to bend and relieve stress on the chip package.

Voids are introduced in a copper shape to reduce warpage experienced by a printed circuit board during a reflow process. Copper shapes on an outer layer of a printed circuit board may be used to connect large packages that include ball grid arrays to the printed circuit board. The copper shapes may induce warpage in the printed circuit board during the reflow process. Routing a mesh pattern of voids in the copper shapes may reduce solder ball joint cracking and pad cratering during reflow and make solder joints more reliable. The voids may make the copper shapes less ridged and change the copper heat dissipation profile to remove sharp warpage forces that cause solder joints to experience pad cratering. The voids may be 8 mil x 8 mil cuts or indentations in the copper shape.

According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

A connection structure for a wiring substrate and a flexible substrate including a wiring substrate and a flexible substrate, in which the wiring substrate includes an insulating member, conductor layer, and ground layer, the flexible substrate includes an insulating sheet and metal film, and the metal film includes a signal line pad joined to the conductor layer via a joining material when viewed from the back surface of the flexible substrate. When viewed from behind the flexible substrate, there is an overlap region where the signal line pad and conductor layer overlap. In a cross-section when the overlap region is cut in a direction perpendicular to a signal transmission direction, in a case where a width of the signal line pad including the overlap region is W, and a width of the conductor layer including the overlap region is W.sub.0, the connection structure satisfies W.sub.0<W.

An interconnect substrate includes a core layer including a resin layer mainly composed of a non-photosensitive thermosetting resin and a through interconnect extending through the resin layer, the core layer having no reinforcement member contained therein, a first interconnect structure laminated on a first side of the core layer and including first interconnect layers and first insulating layers mainly composed of a photosensitive resin, and a second interconnect structure laminated on a second side of the core layer and including second interconnect layers and a single second insulating layer mainly composed of a photosensitive resin, wherein the first interconnect layers are electrically connected to the second interconnect layers via the through interconnect, wherein the core layer has greater rigidity than the first interconnect structure and the second interconnect structure, and wherein a thickness of the second interconnect structure is greater than a thickness of each of the first insulating layer.

A circuit board according to an embodiment includes an insulating layer; a circuit pattern disposed on an upper surface of the insulating layer; a first solder resist disposed on an upper surface of the insulating layer and having a height smaller than a height of the circuit pattern; and a second solder resist disposed on an upper surface of the first solder resist and including a first portion having an upper surface lower than an upper surface of the circuit pattern and a second portion having an upper surface higher than the upper surface of the circuit pattern, wherein the circuit pattern includes: a plurality of first circuit patterns disposed on an upper surface of a first region of the insulating layer, and a plurality of second circuit patterns disposed on an upper surface of a second region of the insulating layer; wherein the first portion of the second solder resist is disposed between the plurality of first circuit patterns to have an upper surface lower than an upper surface of the first circuit pattern; and wherein the second portion of the second solder resist has an upper surface higher than an upper surface of the second circuit pattern, and is disposed to cover the plurality of second circuit patterns between the plurality of second circuit patterns.

A component carrier includes a stack having a first electrically insulating layer structure and a first electrically conductive layer structure arranged on the first electrically insulating layer structure. The first electrically insulating layer structure has at least one first covered portion, which is covered by the first electrically conductive layer structure, and at least one first non-covered portion, which is not covered by the first electrically conductive layer structure. The first electrically insulating layer structure defines a recess at the at least one first non-covered portion.

A printed circuit board includes a coreless substrate including an insulating body and a plurality of core wiring layers disposed on or within the insulating body, a build-up insulating layer covering at least a portion of each of an upper surface and a lower surface of the coreless substrate, and a build-up wiring layer disposed on at least one of an upper surface and a lower surface of the build-up insulating layer. A through-opening penetrates through the insulating body and is configured to receive an electronic component therein, and the first build-up insulating layer extends into the through-opening to embed the electronic component.