Patent classifications
H05K2201/09154
PREPARATION OF SOLDER BUMP FOR COMPATIBILITY WITH PRINTED ELECTRONICS AND ENHANCED VIA RELIABILITY
A process of fabricating a circuit includes providing a first sheet of dielectric material including a first top surface having at least one first conductive trace and a second sheet of dielectric material including a second top surface having at least one second conductive trace, depositing a first solder bump on the at least one first conductive trace, applying the second sheet of dielectric material to the first sheet of dielectric material with bonding film sandwiched in between, bonding the first and second sheets of dielectric material to one another, and providing a conductive material to connect the first solder bump on the at least one first conductive trace to the at least one second conductive trace.
Multi-layer ceramic electronic component, method of producing a multi-layer ceramic electronic component, and substrate with a built-in electronic component
A multi-layer ceramic electronic component includes: a ceramic body including internal electrodes laminated in one axial direction and having a main surface facing in the one axial direction; and an external electrode including a base layer including a step portion formed on the main surface, and a plated layer formed on the base layer, the external electrode being connected to the internal electrodes.
DISPLAY DEVICE, MANUFACTURING APPARATUS OF CHIP ON FILM, AND MANUFACTURING METHOD OF CHIP ON FILM
A display device includes a base film, a driving chip disposed under the base film, a first pad disposed under the base film and connected to the driving chip, and a display panel including a first connection pad connected to the first pad, where one side of the first pad has a first inclined surface which is angled at a first angle with respect to a top surface of the first pad, and the first angle is an acute angle.
Through-hole electrode substrate
A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.
Carrier substrate for electrical, more particularly electronic, components, and method for producing a carrier substrate
A carrier substrate (1) that includes an insulation layer (11) and a metal layer (12), wherein a flank profile (2), in particular an etching flank profile, at least zonally borders the metal layer (12) in a primary direction (P) extending parallel to the main extension plane (HSE), wherein, viewed in the primary direction (P), the flank profile (2) extends from a first edge (15) on an upper side (31) of the metal layer (12), which faces away from the insulation layer (11), to a second edge (16) on a lower side (32) of the metal layer (12), which faces the insulation layer (11), characterized in that the flank profile (2), viewed in the primary direction (P), has at least one local maximum (21) and at least one local minimum (22).
PACKAGE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
A package substrate that prevents breakage of a core substrate is provided. A package substrate includes a core substrate made of a brittle material, at least one insulating layer formed on one surface or both surfaces of the core substrate, and one or more wiring layers formed on the insulating layer and/or in the insulating layer, the core substrate being exposed from an outer peripheral portion of the insulating layer, and the insulating layer being chamfered.
SEMICONDUCTOR PACKAGE WITH GUIDE PIN
A semiconductor guide pin is disclosed. Specific implementations may include a heatsink, one or more substrates coupled together, one or more pressfit pins coupled to the one or more substrates, and two or more guide pins coupled to the one or more substrates, where the two or more guide pins may have a height greater than the one or more pressfit pins.
ELECTRONIC DEVICE
An electronic device is provided. The electronic device includes a flexible circuit board and a conductive adhesive material. The flexible circuit board includes a first conductive layer, an adhesive layer, and a cover layer. The first conductive layer has a top surface, a bottom surface parallel to the top surface and a first side connected between the top surface and bottom surface. The adhesive layer is disposed on the top surface of the first conductive layer. The cover layer is disposed on the adhesive layer. The conductive adhesive material is disposed on the first conductive layer. In addition, the conductive adhesive material is in contact with the first side.
Electrical connector and manufacturing method for the same
An electrical connector and a manufacturing method for the same. The electrical connector comprises a housing member and a plugging module. One end of the housing member is provided with a mating interface. An accommodating space communicating with the mating interface is provided in the housing member. The plugging module comprises a first circuit board, a plurality of electrical conductors and a plurality of first soldering pads. The first circuit board is disposed in the accommodating space. The first circuit board comprises a first surface and a second surface opposite to the first surface. The plurality of electrical conductors are disposed on the first surface and/or the second surface and is close to the mating interface. The plurality of first soldering pads are disposed on the second surface and are electrically connected with the plurality of electrical conductors.
BEVELED OVERBURDEN FOR VIAS AND METHOD OF MAKING THE SAME
A substrate including a via with a beveled overburden is disclosed. The substrate can include a substrate having a first surface, a second surface opposite the first surface, and a via passing from the first surface to the second surface. The via can be coated with a metallic layer that includes a first beveled overburden on the first surface, and the first beveled overburden can include a first outer edge that forms a first bevel angle greater than 95° with the first surface. The substrate can include a second beveled overburden that includes a second outer edge that forms a second bevel angle greater than 95° with the second surface. Methods of making the beveled overburdens are also disclosed.