A package structure includes a substrate, an insulator, a plurality of pads and a patterned circuit layer. The substrate includes a plurality of through holes. The insulator covers the substrate and is filled in the through hole. The conductive vias are located in the through holes and penetrate the insulator filled in the through holes. The pads are disposed on an upper surface and a lower surface of the insulator and electrically connected to the conductive vias. A bottom surface of each pad is lower than the top surface of the insulator. The patterned circuit layer is disposed on the top surface of the insulator and connected to the conductive vias and the pads. A bottom surface of the patterned circuit layer is lower than the top surface of the insulator.

A golden finger and a board edge interconnecting device are disclosed. The golden finger includes a printed circuit board (PCB) surface layer and at least one PCB inner layer, where a metal foil of the PCB inner layer is connected to a metal foil of the PCB surface layer through a current-carrying structure, so that a current-carrying channel of the golden finger passes through the PCB surface layer and the PCB inner layer. The board edge interconnecting device includes the foregoing golden finger. In the embodiments, a current-carrying capacity of a PCB in the golden finger is increased without increasing a size and thickness of a copper foil of the PCB in the golden finger, thereby effectively improving the current-carrying capacity of the PCB in the golden finger.

An ESD protection device 1 has a ceramic insulating material 10, first and second discharge electrodes 21 and 22, and a discharge-assisting section 51. The first and second discharge electrodes 21 and 22 are disposed somewhere of the ceramic insulating material 10. The discharge-assisting section 51 is located between the distal end portion of the first discharge electrode 21 and the distal end portion of the second discharge electrode 22. The discharge-assisting section 51 is an electrode configured to reduce the discharge starting voltage between the first discharge electrode 21 and the second discharge electrode 22. The discharge-assisting section 51 is made from a sintered body containing conductive particles and at least one of semiconductor particles and insulating particles. The first and second discharge electrodes contain at least one of the semiconductor material constituting the semiconductor particles and the insulating material constituting the insulating particles.

An embedded device 105 is assembled within a flexible circuit assembly 30 with the embedded device mid-plane intentionally located in proximity to the flexible circuit assembly central plane 115 to minimize stress effects on the embedded device. The opening 18, for the embedded device, is enlarged in an intermediate layer 10 to enhance flexibility of the flexible circuit assembly.

A wiring board includes a plurality of wiring layers, a plurality of insulating layers, and an electrode member made of a conductive material, the electrode member being incorporated in the wiring board in a state in which the electrode member includes exposed sections on side surfaces that cross the plurality of wiring layers and the plurality of insulating layers.

A semiconductor package includes a substrate including a core layer having a first surface and a second surface which is opposite to the first surface, a wiring layer formed over the first and second surfaces and in an inside of the core layer, and having a first electrode disposed in the inside of the core layer and exposed from the core layer and a second electrode disposed over the first surface, and a passivation layer formed over the first and second surface of the core layer such that the first and the second electrodes are exposed; a first semiconductor chip disposed over the first surface of the core layer; a second semiconductor chip stacked over the first semiconductor chip; a first connection member for connecting the first semiconductor chip with the first electrode; and a second connection member for connecting the second semiconductor chip with the second electrode.

An electronic unit (1) having a circuit board, PCB, (2) arranged to be mounted in a main housing (6, 7 and having a first housing part (6) and a second housing part (7), where the first housing part (6) is at least partly electrically conducting. The PCB (2) having a first outer layer (3), a second outer layer (4), and a ground plane (5). The first outer layer (3) faces the first housing part (6) and the second outer layer (4) faces the second housing part (7) The ground plane (5) is in electrical contact with the first housing part (6) forming a first chamber (29), facing the first outer layer (3), and a second chamber (30), facing the second outer layer (4). The chambers (29, 30) are separated by the ground plane (5), providing electromagnetic shielding between the chambers (29, 30).

A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal plane provided in the dielectric material, the first metal plane being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via, and a second metal plane provided n or on the dielectric material in parallel with the extension direction of the penetrating via, the second metal plane connected to the first metal plane.

A PCB underneath the display panel includes a plurality of insulation layers and one or more metal layers disposed between two adjacent insulation layers out of the plurality of insulation layers. A lower structure is disposed between the display panel and the PCB. At least a portion of a metal layer among the one or more metal layers that is most adjacent to the lower structure is exposed, and the lower structure is electrically connected to the exposed portion of the metal layer. Such exposed portion of the metal layer is electrically connected to the lower structure, so that the area where the PCB is referenced to the ground potential is increased. As a result, residual voltage, residual current in the PCB and noise caused by electromagnetic fields generated thereby can be reduced.

A system for transmitting or receiving signals may include a dielectric substrate having a major face, a communication circuit, and an electromagnetic-energy directing assembly. The circuit may include a transducer configured to convert between RF electrical and RF electromagnetic signals and supported in a position spaced from the major face of the substrate operatively coupled to the transducer. The directing assembly may be supported by the substrate in spaced relationship from the transducer and configured to direct EM energy in a region including the transducer and along a line extending away from the transducer and transverse to a plane of the major face.