Techniques for reducing multi-reflection noise via compensation structures are described herein. An example system includes a capacitive component. The example system further includes a capacitive compensation structure coupled to two ends of the capacitive component. The example system includes a partially meshed ground plane coupled to one side of a dielectric substrate. The example system also includes one or more signal conductors coupled to another side of the dielectric substrate and electrically coupled to the capacitive component. The one or more signal conductors are located parallel to a meshed length of the partially meshed ground plane.

A semiconductor device according to an embodiment has a first semiconductor component and a second semiconductor component which are electrically connected with each other via an interposer. The interposer has a plurality of first signal wiring paths, and a plurality of second signal wiring paths each having a path distance smaller than each of the plurality of first signal wiring paths. Furthermore, the first semiconductor component includes a first electrode, a second electrode, and a third electrode arranged in order in a first direction. Furthermore, the second semiconductor component includes a fourth electrode, a fifth electrode, and a sixth electrode arranged in order in the first direction. Furthermore, the first electrode is connected with the fourth electrode via the first signal wiring path, the second electrode is connected with the fifth electrode via the first signal wiring path, and the third electrode is connected with the sixth electrode via the first signal wiring path.

A circuit board according to an embodiment includes an insulating layer including a first region and a second region; a circuit pattern disposed on an upper surface of the first region and an upper surface of the second region of the insulating layer; and a solder resist including a first portion disposed on the upper surface of the first region of the insulating layer and a second portion disposed the upper surface of the second region; wherein a height of the first portion of the solder resist is smaller than a height of the circuit pattern, wherein a height of the second portion of the solder resist is greater than the height of the circuit pattern, wherein at least one of the first region and the second region is divided into a plurality of partial regions, wherein at least one of the first portion and the second portion of the solder resist has a different height in the plurality of partial regions.

A circuit structure includes a low-density conductive structure, a high-density conductive structure and a plurality of traces. The high-density conductive structure is disposed over the low-density conductive structure, and defines an opening extending from a top surface of the high-density conductive structure to a bottom surface of the high-density conductive structure. The opening exposes a first pad of the low-density conductive structure and a second pad of the low-density conductive structure. The second pad is spaced apart from the first pad. The traces extend from the top surface of the high-density conductive structure into the opening. The traces include a first trace connecting to the first pad of the low-density conductive structure and a second trace connecting to the second pad of the low-density conductive structure.

Embodiments disclosed herein include an interposer. In an embodiment, the interposer comprises a substrate, where the substrate comprises a glass layer. In an embodiment, a trace is on the substrate, where the trace has a bottom surface, sidewall surfaces, and a top surface. In an embodiment, the sidewall surfaces and the top surface are exposed to air. In an embodiment, a trench into the substrate is adjacent to at least one sidewall surface of the trace.

A transmission line portion of a flat cable includes first regions and second regions connected alternately. In the first region, the transmission line portion is a flexible tri-plate transmission line including a dielectric element including a signal conductor, a first ground conductor including opening portions, and a second ground conductor which is a solidly filled conductor. In the second region, the transmission line portion is a hard tri-plate transmission line including a wide dielectric element including a meandering conductor, and a first ground conductor and a second ground conductor which are solidly filled conductors. A variation width of the characteristic impedance in the second region is larger than a variation width of the characteristic impedance in the first region.

A wiring board of an electronic device includes: a board terminal connected to a semiconductor device (semiconductor component); a wire formed in a first wiring layer and electrically connected to the board terminal; a conductor pattern formed in a second wiring layer and electrically connected to the wire via a via wire; and another conductor pattern formed in a third wiring layer and supplied with a first fixed potential. The conductor pattern and the another conductor pattern face each other with an insulating layer interposed therebetween, and an area of a region where the conductor pattern and the another conductor pattern face each other is larger than an area of the wire.

An electronic component (11) is embedded in an end portion of a surface (P1) and an end portion of a surface (P2) adjacent to each other in a three-dimensional base (2). The portion of an electrode (21) exposed from the surface (P1) and an electrode (101) of a packaged IC (41) are connected to each other via a wiring line (201). The portion of the electrode (21) exposed from the surface (P2) and an electrode (25) of an electronic component (15) are connected to each other via a wiring line (202). Accordingly, it is possible to realize a three-dimensional circuit structure requiring no wiring line spanning over or along an end portion thereof.

A circuit board includes a substrate and multiple pads. The multiple pads are disposed on the substrate and have respective footprints for connecting one or more electronic components to the circuit board, at least a pad from among the pads includes a linear electrical trace laid out in a two-dimensional (2D) pattern that covers at least a part of a footprint of the pad.

The device intended to be thermoformed comprises a substrate capable of being thermoformed and an electrically conductive member integral with the said substrate. The electrically conductive member comprises: electrically conductive particles, an electrically conductive material, electrically conductive elements of elongated shape. The electrically conductive material has a melting point which is strictly less than the melting point of the electrically conductive particles and than the melting point of the elements of elongated shape.