A circuit board includes an open substrate and a heat dissipation block. The open substrate includes a substrate body, an opening and at least one first fixing portion and at least one second fixing portion. The substrate body has a top surface and a bottom surface. The opening is in the substrate body and has a first sidewall and a second sidewall opposite to the first sidewall. The first fixing portion and the second fixing portion extends from the substrate body toward the opening, in which the first fixing portion and the second fixing portion are respectively protruded from the first sidewall and the second sidewall. The heat dissipation block is directly clamped between the first fixing portion and the second fixing portion.

Disclosed herein is a circuit board that includes a resin substrate including a substrate wiring layer, and an electronic component embedded in the resin substrate and having a plurality of external electrodes. The resin substrate includes a plurality of via holes that expose the external electrodes and a plurality of via conductors embedded in the via holes to electrically connect the substrate wiring layer to the external electrodes. At least some of the via holes are different in planar shape from each other.

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.

The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

A method of manufacturing a circuit substrate includes forming, in an insulating substrate and circuit patterns that are provided on a first surface and a second surface of the insulating substrate, a through-hole penetrating the insulating substrate and the circuit patterns, where the circuit patterns contain Cu as a main component. The method includes filling, in the through-hole, an electrically conductive paste that is a melting-point shift electrically conductive paste including SnBi solder powder, Cu powder, and resin, and forming a protrusion obtained by causing the electrically conductive paste to protrude from the through-hole. The method further includes performing pressure treatment on the protrusion near the through-hole; and performing heat treatment on the insulating substrate whose protrusion is subjected to the pressure treatment and causing the circuit patterns and the electrically conductive paste to be electrically connected with each other.

The present disclosure provides a circuit board. The circuit board may include a number of stacked core boards each having a top surface. At least part core boards of the number of stacked core boards may include circuit layers at top surfaces thereof. A groove may be defined through the at least part core boards. A conductive material may be received in the groove configured to couple to the circuit layers of at least two core boards. A cross section of the groove may include a length in a first direction and a length in a second direction, and the length in the first direction may be greater than the length in the second direction. Electroplating solution may capable of contacting any portions of the groove to electroplate, to form the conductive material.

Systems and methods are provided for reducing crosstalk between differential signals in a printed circuit board (PCB) using fine pitch vias. A pair of contact pads are on the top surface of the PCB and configured to couple a PCB component to the PCB, the contacts a first distance from each other. A first via of a plurality of vias is electrically coupled to a first contact of the pair of contacts and a second via is electrically coupled to a second contact, the first via and second via a second distance from each other, the second distance being less than current standards for minimum via pitch. Each via comprises a via pad on the top surface and a plated through-hole extending from the top surface to a termination point. A separator gap is between the first via and the second via.

A timing control (TCON) board and a display device are provided. The TCON board includes a TCON chip and a CB. A plurality of heat dissipating terminals are provided to commonly connect the TCON chip to the CB, increasing a total contact area of the TCON board and the CB. Therefore, heat dissipation efficiency of the TCON chip is improved. At the same time, the heat dissipating terminals greatly reduce a pseudo connection percentage. Hence, heat dissipation performance and electrical performance of the entire TCON chip are avoided to be impacted.

A component carrier includes an electrically insulating layer structure having a first main surface and a second main surface with a through hole extending through the electrically insulating layer structure between the first main surface and the second main surface. An electrically conductive bridge structure connects opposing sidewalls of the electrically insulating layer structure delimiting the through hole. A vertical thickness of the electrically insulating layer structure is not more than 200 m and a narrowest vertical thickness of the bridge structure is at least 20 m.

A disclosed method for manufacturing a printed circuit board includes creating multiple conductive layers, each including conductive traces for carrying high-speed data signals, and a non-round plated through power via for delivering high current from a switched-mode power source to and between the conductive layers. Creating the power via may include drilling an opening through the multiple conductive layers, the perimeter of which has a flattened oval shape, and plating the walls of the opening to a predetermined plating thickness using a conductive material. The power via may have a lower resistivity than a combined resistivity of multiple round, plated through vias that, together with required spacing between them, have the same footprint as the power via. The space occupied by the power via may be less than a required footprint for multiple round, plated through vias whose combined resistivity equals the resistivity of the power via.