A printed wiring board includes a resin insulating layer, a projecting conductor layer formed on a surface of the resin insulating layer such that the projecting conductor layer is projecting from the surface of the resin insulating layer, and an integral conductor structure formed in the resin insulating layer and including a via conductor portion and an embedded conductor layer portion such that the embedded conductor layer portion is embedded in the resin insulating layer on the opposite side of the resin insulating layer with respect to the projecting conductor layer and has an exposed surface exposed from the resin insulating layer and the via conductor portion is formed through the resin insulating layer and is connecting the embedded conductor layer portion and projecting conductor layer. The projecting conductor layer and integral conductor structure are formed such that the projecting conductor layer and integral conductor structure are individual conductor structures.

A printed circuit board includes a plurality of layers including conductive layers separated by dielectric layers; and at least one via configured for solder attachment to a connector lead of a surface mount connector, the at least one via including a conductive element that extends from an upper surface of the printed circuit board through one or more of the plurality of layers, the conductive element having a recess in a surface thereof. The recess is configured to receive a tip portion of the connector lead of the surface mount connector. The printed circuit board may have via patterns including signal vias and ground vias.

A wiring board includes a board including a core, a conductive layer on the core, and a laminated structure over the core and conductive layer, and a stacked structure formed in the board and including a through-hole conductor through the core and a via conductor in the laminated structure. The through-hole conductor has though-hole portion through the core and land portion on the core, the laminated structure includes an insulation layer in which the via conductor is formed, the via conductor is stacked on the land portion such that the stacked structure including the through-hole and via conductors is formed through the core and the insulation layer, and the stacked structure is formed such that the through-hole portion has end connected to the land portion and the end has width set greater than width of bottom of the via conductor and smaller than width of top of the via conductor.

A semiconductor storage device includes a first substrate including a first layer and a second layer on the first layer, a memory chip on the first layer, a controller disposed on the first layer and configured to control the memory chip, and molding resin that covers the first layer, the memory chip, and the controller. The second layer of the first substrate includes a conductive pattern including a plurality of terminals, and an insulating layer partially covering the conductive pattern and the first layer, and at a part of the first layer not covered by the insulating layer, one or both of the conductive pattern and the insulating layer form first concaves at predetermined intervals.

A mounting substrate includes a through-hole 13 formed in a substrate 10, a first land part 21, a second land part 31, a first component attaching part 22, a second component attaching part 32, a conductive layer 14, and a filling member 15 filled into a part of the through-hole 13. A shortest distance allowable value L.sub.0 from the center of the first land part 21 to a component 51 is determined on the basis of the volume V.sub.h of a part of the through-hole 15 positioned above a top surface of the filling member 15 on the side of the first land part 21, the length L.sub.1 of the component 51 to be mounted to the first component attaching part 22, and the maximum allowable value of the inclination of the component 51 to be mounted to the first component attaching part 22 relative to the first surface 11 of the substrate 10.

An electronic device is provided, including an electronic element, and a protective substrate. The protective substrate includes a concave portion, and a flat portion. The concave portion has a concave surface and a convex surface that is opposite to the concave surface. The flat portion is connected to the concave portion. The electronic element overlaps the concave portion and is arranged under the convex surface.

A resin multilayer substrate includes a resin insulating layer, first and second conductor layers, and an interlayer connection conductor penetrating the resin insulating layer in a stacking direction of the first and second conductor layers and connecting the first and second conductor layers. The interlayer connection conductor includes first and second portions. The first portion has lower conductivity than the second portion. The first conductor layer is not in contact with the second portion. The second conductor layer is in contact with the second portion. A distance between two corner portions at which a distal end portion of the second portion is most separated is longer than a distance between two corner portions at which a proximal end portion of the second portion is in contact with the second conductor layer.