A process for improving the performance of the sliding rheostat of 5G communication high-frequency signal board with the sliding rheostat slides along between two bonding pads, includes the following steps: outer layer etching; resin plugging: a. plugging the resinous ink into the pre-plugging position; b: baking, baking on the baking plate of the oven after the plugging is finished; board polishing: using a ceramic brush to process the plugged board, then using a non-woven fabric blush to polish the surface that is polished by ceramic brush. The present invention provides a process for improving the performance of the sliding rheostat of 5G communication high-frequency signal board. The resin plugging method is used to plug the gap between the conductors of the sliding rheostat, so as to prevent the sliding rheostat from being unable to slide due to the altitude difference between conductors of the high-frequency signal board.

A transmission line device includes a first multilayer substrate with a transmission line including laminated insulating base materials and a conductor pattern on the insulating base materials, and a second multilayer substrate defining a connected member to which the transmission line of the first multilayer substrate is connected. The conductor pattern includes a signal conductor pattern and a signal electrode pad electrically connected to the signal conductor pattern. The first multilayer substrate includes a resist film provided on a surface of a laminate of the insulating base materials, and the resist film includes an opening that is separated from an outer edge of the signal electrode pad in a surface direction of the laminate of the insulating base material and exposes the signal electrode pad.

A method for producing a metal-ceramic substrate includes attaching a metal layer to a surface side of a ceramic layer, the metal layer being structured into a plurality of metallization regions respectively separated from one another by at least one trench-shaped intermediate space to form conductive paths and/or connective surfaces and/or contact surfaces. The method further includes filling the at least one trench-shaped intermediate space with an electrically insulating filler material, and covering first edges of the metallization regions facing and adjoining the surface side of the ceramic layer in the at least one trench-shaped intermediate space, as well as at least one second edge of the metallization regions facing away from the surface side of the ceramic layer in the at least one trench-shaped intermediate space, by the electrically insulating filler material.

A printed circuit board according to one embodiment of the present invention comprises an insulation board and a plurality of metal electrodes disposed on the insulation board, wherein: the plurality of metal electrodes include a first electrode and a second electrode; the first electrode includes a first surface parallel to an upper surface of the insulation board, a second surface facing the first surface, a first side surface disposed between the first surface and the second surface, and a second side surface facing the first side surface; a part of the first side surface and a part of the second side surface protrude toward the outside of the first electrode in the direction parallel to the upper surface of the insulation board; the first side surface protrudes farther in an area adjacent to the first surface than in an area adjacent to the second surface; and the second side surface protrudes farther in the area adjacent to the second surface than in the area adjacent to the first surface.

A circuit board according to the present disclosure includes a substrate, a conductor layer arranged on the substrate, a reflective layer arranged on the conductor layer, and a silicone-resin layer arranged on the substrate. The silicone-resin layer is in contact with the conductor layer and the reflective layer. The silicone-resin layer contains equal to or more than 45% by mass of a plurality of fillers. A first filler whose aspect ratio is larger than 5 occupies equal to or more than 5% of 100% of a total number of the fillers.

A method for manufacturing a high-current printed circuit board, comprising: providing a circuit substrate comprising a substrate layer; a first circuit layer formed on the substrate layer; and a second circuit layer formed on the substrate layer and facing away from the first circuit layer, wherein first conductive circuits are defined on the first circuit layer, second conductive circuits are defined on the second circuit layer, and a line width of each of the first conductive circuits is greater than a line width of each of the second conductive circuits; and forming buffering circuits by plating, wherein the buffering circuits are electrically connected the first circuit layer to the second circuit layer; wherein a line width of each of the buffering circuits is greater than the line width of each of the second conductive circuits.

A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.

The present application discloses a filtering cable, which solves the problem that the cable in the related art cannot ensure a simple and reasonable structural design while having good filter performance. One or several core wires and N defective conductor layers surrounding the core wires are sequentially provided from inside to outside in the cross section in the radial direction of the filtering cable; wherein the defective conductor layer has an etching pattern; the etching pattern is distributed in the axial direction of the filtering cable; the etching pattern is used to make the filtering cable equivalent to a preset filter circuit to filter the signal transmitted in the filtering cable.

A printed circuit board includes a circuit substrate and a plurality of buffering circuits. The circuit substrate includes a substrate layer, and first and second circuit layers formed on either side of the substrate layer. The first circuit layer comprises a plurality of first conductive circuits. The second circuit layer comprises a plurality of second conductive circuits. A line width of each of the plurality of first conductive circuits is greater than a line width of each of the plurality of second conductive circuits. The plurality of buffering circuits electrically connect the first circuit layer to the second circuit layer and a line width of each of the plurality of buffering circuits is greater than the line width of each of the plurality of second conductive circuits.

A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.