A resin multilayer substrate includes a substrate main body including first, second, and third wiring portions connected to one another by a connecting portion. First, second and third external connection terminals are respectively included in the first, second and third wiring portions. The first external connection terminal includes a conductor exposed at a surface of the substrate main body. The second and third external connection terminals include connectors mounted on conductors on the surface of the substrate main body. An auxiliary mounting conductor is disposed between the first external connection terminal and the second and third external connection terminals on the surface of the substrate main body.

An electronic circuit includes: a motherboard; an input/output connector including at least one group containing N input/output contacts; a set containing expansion slots having expansion contacts electrically connected to input/output contacts; each input/output contact being identified by an identifier T, each expansion slot being identified by an identifier S, each connected expansion contact being identified by an identifier R, for: each expansion slot of identifier S; and each connected expansion contact of identifier R. Each input/output contact of identifier T is electrically connected to a single expansion contact of identifier R of the expansion slot of identifier S, and the identifier T is calculated according to the following relation: T[(R+DS) modulo (N)], where D is fixed in each group and is an integer sub-multiple of the natural number N.

A resin multilayer substrate includes a substrate main body including first, second, and third wiring portions connected to one another by a connecting portion. First, second and third external connection terminals are respectively included in the first, second and third wiring portions. The first external connection terminal includes a conductor exposed at a surface of the substrate main body. The second and third external connection terminals include connectors mounted on conductors on the surface of the substrate main body. An auxiliary mounting conductor is disposed between the first external connection terminal and the second and third external connection terminals on the surface of the substrate main body.

A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.

An anisotropic conductive film has a structure in which high hardness conductive particles having a 20% compression elastic modulus of 8000 to 28000 N/mm.sup.2 and low hardness conductive particles having a lower 20% compression elastic modulus than that of the high hardness conductive particles are dispersed as conductive particles in an insulating resin layer. The number density of all the conductive particles is 6000 particles/mm.sup.2 or more, and the number density of the low hardness conductive particles is 10% or more of that of all the conductive particles.

A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.

A circuit substrate module includes: a plurality of substrates which are arranged in a matrix, and on at least some of which circuit components are mounted; a plurality of first flexible substrates each of which is arranged between two adjacent substrates in a row direction among the plurality of substrates, and connects the two adjacent substrates; and a plurality of second flexible substrates each of which is arranged between two adjacent substrates in a column direction among the plurality of substrates, and connects the two adjacent substrates.

A resin multilayer substrate includes a substrate main body including first, second, and third wiring portions connected to one another by a connecting portion. First, second and third external connection terminals are respectively included in the first, second and third wiring portions. The first external connection terminal includes a conductor exposed at a surface of the substrate main body. The second and third external connection terminals include connectors mounted on conductors on the surface of the substrate main body. An auxiliary mounting conductor is disposed between the first external connection terminal and the second and third external connection terminals on the surface of the substrate main body.

An example stretchable device is described that includes electrical contacts and an interconnect coupling the electrical contacts. The interconnect has a meander-shaped configuration that includes at least one nested serpentine-shaped feature. The interconnect can be conductive or non-conductive. The meander-shaped configuration can be a serpentine structure, providing a serpentine-in-serpentine configuration.

A substrate for mounting a semiconductor device includes an insulating layer having first and second opposed surfaces defining a thickness. First and second electrically conductive lands are included in the insulating layer. The first electrically conductive lands extend through the whole thickness of the insulating layer and are exposed on both the first and second opposed surfaces. The second electrically conductive lands have a thickness less than the thickness of the insulating layer and are exposed only at the first surface. Electrically conductive lines at the first surface of the insulating layer couple certain ones of the first electrically conductive lands with certain ones of the second electrically conductive lands. The semiconductor device is mounted to the first surface of the insulating layer. Wire bonding may be used to electrically coupling the semiconductor device to certain ones of the first and second lands.