Capacitor assembly, comprising a printed circuit board comprising a first conductive trace and a second conductive trace, and a first row of capacitors comprising a plurality of surface mounted capacitor elements. Each of the plurality of surface mounted capacitor elements comprises a pair of outer electrodes, one of the pair being mounted to the first conductive trace and defining a first junction, and the other one being mounted to the second conductive trace defining a second junction. The first junction and the second junction define a first capacitor longitudinal axis. The first conductive trace has a first current flow direction with a first oblique angle relative to the first capacitor longitudinal axis.

A high frequency amplifier includes an asymmetric Doherty amplifier configured to amplify a high frequency signal having a wavelength A, the high frequency signal being input, and the asymmetric Doherty amplifier including a carrier amplifier and a peak amplifier, the peak amplifier being configured to start an amplifying operation when an output of the carrier amplifier reaches a saturation region and having a saturation output different from a saturation output of the carrier amplifier, a driver amplifier configured to drive the asymmetric Doherty amplifier, a branch circuit configured to branch the high frequency signal amplified by the driver amplifier into an input path on a peak amplifier side and an input path on a carrier amplifier side, a phase adjustment circuit configured to delay either a phase of a signal input to the peak amplifier or a phase of a signal input to the carrier amplifier, the phase adjustment circuit being provided on either the input path on the peak amplifier side or the input path on the carrier amplifier, a first substrate on which the carrier amplifier and the peak amplifier are mounted, and a second substrate on which the driver amplifier, the branch circuit, and the phase adjustment circuit are mounted. An input terminal of the driver amplifier and an input terminal of the carrier amplifier are disposed at positions where the input terminal of the driver amplifier and the input terminal of the carrier amplifier project to each other when the second substrate is stacked on the first substrate. An electrical length from the input terminal of the driver amplifier to an output terminal of the carrier amplifier is set to a phase of (2n+1)×π, where n is an integer greater than or equal to 0.

A multilayer ceramic capacitor includes a capacitor main body including a multilayer body and external electrodes, the multilayer body including dielectric layers and internal electrode layers stacked alternately, each of the external electrodes being provided on an end surface in a length direction of the multilayer body and being connected to the internal electrode layers, and two interposers on one surface in a stacking direction of the capacitor main body and spaced apart from each other in the length direction, the interposers including bonding surfaces bondable to the one surface of the capacitor main body and including inner edge portions which are opposite to each other and each having a length longer than a length in a width direction of the multilayer body.

A capacitor packaging having a central termination and three or more capacitors (or groups of capacitors) arranged about the central termination. The electrical flow paths between the termination and the capacitors or groups of capacitors are of substantially the same length. The capacitors or groups of capacitors may be arranged in a generally circular pattern with the termination centered on the center. The termination may include first and second terminals. The capacitors may be mounted to a printed circuit board (“PCB”) with traces on opposite surfaces of the PCB providing electrical flow paths from the terminals to opposite legs of the capacitors. The capacitor packaging may include a primary PCB with a first circular arrangement of capacitors and a secondary PCB with a second circular arrangement of capacitors. The capacitors may be sandwiched between the PCBs with the second arrangement of capacitors disposed concentrically inwardly of the first arrangement.

A discrete electrical component is disclosed, including a component member having at least one lead; and a base member on which the component member is supported. The electrical component further includes at least one compliant pin member, each compliant pin member having a first end portion configured for press-fit engagement in a printed circuit board and a second end portion electrically connected to the at least one lead of the component member. The at least one compliant pin at least partly extends through or into the base member.

An electronic component and a board having the same mounted thereon are provided. The electronic component includes an electronic component including a capacitor array in which a plurality of multilayer capacitors including a capacitor body and a pair of external electrodes, respectively disposed on both end portions of the capacitor body in a first direction, are stacked in a second direction, perpendicular to the first direction, and a length of a multilayer capacitor, disposed on a lower end in the second direction, in the first direction is less than a length of another multilayer capacitor in the first direction; and a pair of metal frames, respectively disposed to be connected to the pair of external electrodes of the multilayer capacitor disposed on the lower end.

Power electronics arrangement including a printed circuit board and at least one power module fastened on the printed circuit board, which has one or more electronic components potted by a potting compound. At least one module connecting point of the power module is electrically contacted with at least one board connecting point of the printed circuit board by an electrically conductive pin. A base section of the pin is fastened on the module connecting point or on the board connecting point, and the end of the pin opposite to the base section is pressed in the installation position into a contacting opening assigned or assignable to the respective other connecting point.

Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.

The electronic module including a metal base, a ceramic substrate, and a die-capacitor is disclosed. The ceramic substrate is mounted on the metal base via eutectic solder. The ceramic substrate includes a main substrate having a back surface facing the metal base and a front surface opposite to the back surface, and a back metal layer placed on the back surface of the main substrate and joined to the eutectic solder. The die-capacitor is mounted on the front surface of the ceramic substrate along one edge of the ceramic substrate. The back surface of the ceramic substrate is provided with an exposure region where the back metal layer is not provided. The exposure region includes a main region corresponding to an outer shape of the die-capacitor spreading along the front surface and an edge region extending from the main region to the one edge of the ceramic substrate.

A semiconductor-based capacitor can include a substrate including a semiconductor material, an oxide layer formed on a surface of the substrate, a conductive layer formed over at least a portion of the oxide layer, a plurality of distinct coplanar upper terminals, and at least one lower terminal formed. Each of the upper terminals and the at least one lower terminal can be exposed along the top and bottom surfaces of the substrate, respectively, for embedding the capacitor in a substrate such as a circuit board. The semiconductor-based capacitor can be sufficiently miniaturized to be embeddable within a circuit board while providing superior capacitance values. For example, a ratio of the length to the width of the substrate can be in a range from about 3:1 to about 1:3 and an area of the substrate can be less than about 3 mm.sup.2.