A circuit board assembly for electronic devices includes a circuit board having a first surface and a second surface opposite the first surface, and a heat sink carrier disposed on the first surface of the circuit board. The heat sink carrier includes at least one clamp portion. The assembly also includes a heat sink. The heat sink is positioned in the at least one clamp portion of the heat sink carrier to transfer heat from one or more electronic devices to the heat sink via the heat sink carrier.

Provided is a power conversion circuit for achieving a power conversion device capable of suppressing charging/discharging of a parasitic capacitor caused by high-frequency switching, and of reducing a loss of a semiconductor switching element. The power conversion circuit includes: a circuit board including a plurality of layers including two or more layers, on which circuit patterns are formed; and a plurality of semiconductor switching elements connected to the circuit patterns of the circuit board, and configured to perform switching for power conversion. In the circuit board, a plurality of control ground patterns for different nodes, which are configured to drive the plurality of semiconductor switching elements, are arranged so as not to overlap one another in plan view.

An electronic circuit has three circuit carriers and two semiconductor components. A first semiconductor component contacts with its upper side an underside of a first circuit carrier, and with its underside an upper side of a second circuit carrier. The first circuit carrier has vias, with a first via connecting the first semiconductor component to a first conducting path and a second via connecting a connection element forming a second conducting path providing an integral connection between the circuit carriers. A second semiconductor component contacts the underside of the first circuit carrier and is electrically connected to the first or second conducting path. An underside of the second semiconductor component contacts an upper side of the third circuit carrier. A lateral thermal expansion coefficient of the first circuit carrier is greater than a lateral thermal expansion coefficient of both the second and the third circuit carrier.

A semiconductor package includes a circuit structure, a first redistribution layer, a second redistribution layer, a first encapsulant, a bus die and a plurality of through vias. The first redistribution layer is disposed over the circuit structure. The second redistribution layer is disposed over the first redistribution layer. The first encapsulant is disposed between the first redistribution layer and the second redistribution layer. The through vias surround the bus die. The first encapsulant is extended along an entire sidewall of the bus die, and a first surface of the bus die is substantially coplanar with top surfaces of the first encapsulant and the plurality of through vias.

A laminate having an integrated electrical component disposed within the laminate is disclosed. The laminate includes a first paper layer having at least first and second vias through the first paper layer; a first electrically-conductive layer, comprising an electrically-conductive material, disposed over a portion of the first paper layer; a second electrically-conductive layer, comprising the electrically-conductive material, disposed over another portion of the first paper layer; an electrical component disposed over the first and second electrically-conductive layers; and an insulating layer disposed over the electrical component. The first paper layer and the insulating layer encapsulate the first electrically-conductive layer, the second electrically-conductive layer, and the electrical component. The first and second vias are in electrical contact with the first electrically-conductive layer and a first terminal of the electrical component, and with the second electrically-conductive layer and a second terminal of the electrical component, respectively.

The disclosed technology relates to a power supply circuit that utilizes a double-sided printed circuit board (PCB) that has a first surface and a second surface. The second surface is disposed opposite the first surface. Mounted on the first surface is a first power stage and a first inductor. Mounted on the second surface is a second power stage and a second inductor. The second power stage is disposed opposite the first power stage. The second inductor is disposed opposite the first inductor.

An electronic device includes a substrate, a plurality of conductive patterns, and a tunable element. A plurality of conductive patterns are disposed on the substrate. The tunable element is disposed on at least one conductive pattern in the plurality of conductive patterns and includes a first pad, a second pad, and a third pad. The first pad, the second pad, and the third pad are separated from each other. The first pad and the second pad are overlapped with the at least one conductive pattern in the plurality of conductive patterns. The third pad is disposed between the first pad and the second pad.

A power module includes at least one power semiconductor element between first and second conductive layers, a first cooling member on the first conductive layer, a second cooling member under the second conductive layer, and at least one snubber capacitor between the first and second conductive layers. Each snubber capacitor has a capacitor core between first and second electrodes and first and second transition layers. The first transition layer is between the first conductive layer and the first electrode and the second transition layer is between the second electrode and the second conductive layer, or the first transition layer is between the first electrode and the capacitor core and the second transition layer is between the capacitor core and the second electrode. The first and second transition layers are conductive. A thermal expansion coefficient of the transition layers is between thermal expansion coefficients of adjacent elements of the snubber capacitor.

A bi-directional solid state switch includes: a first bus bar; a second bus bar; a first solid state switch implemented on a first printed circuit board (PCB), the first solid state switch including: a first control terminal; a first terminal electrically connected to the first bus bar; and a second terminal; and a second solid state switch implemented on a second PCB, the second solid state switch including: a second control terminal; a third terminal electrically connected to the second terminal of the first solid state switch; and a fourth terminal electrically connected to the second bus bar.