A display panel includes a plastic substrate and a first inner lead bonding (ILB) electrode on the plastic substrate. The first ILB electrode includes a first bonding segment, a second bonding segment, and a first connection segment. The first bonding segment is extended in a first direction oblique to a vertical direction of the display panel. The first connection segment is configured to provide an electrical connection between the first bonding segment and the second bonding segment. The first bonding segment is configured to be bonded to a first display driver integrated circuit (DDIC) chip, and the second bonding segment is configured to be bonded to a second DDIC chip configured differently from the first DDIC chip.

Embodiments herein describe a capillary containing a eutectic conductive liquid (e.g., EGaIn) and an electrolyte (e.g., NaOH) that is integrated into a printed circuit board (PCB). In one embodiment, the PCB includes a capillary, a negative electrode, a positive electrode, a plurality of insulation layers, and a conductive layer. The capillary extends through the PCB. The capillary includes a side surface forming an annular cylinder. A eutectic conductive liquid and an electrolyte are disposed within an aperture formed by the side surface. An electrode extends through the side surface and contacts at least the eutectic conductive liquid or the electrolyte. The negative electrode is disposed at a first end of the capillary. The positive electrode is disposed at a second end of the capillary. The conductive layer is disposed between two of the plurality of insulation layers. The electrode forms an electrical connection with the conductive layer.

An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.

An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.

In an example, a device includes: a printed circuit board (PCB); at least one solid state drive (SSD) connected at a first side of the PCB via at least one SSD connector; at least one field programmable gate array (FPGA) mounted on the PCB at a second side of the PCB; and at least one connector attached to the PCB at a third side of the PCB, wherein the device is configured to operate in a first speed from a plurality of operating speeds based on a first input received via the at least one connector.

An integrated circuit may include a printed circuit board and multiple processor sockets on the printed circuit board. Each of the multiple processor sockets is operable to receive a microprocessor and a programmable device. When a microprocessor is placed in a processor socket, that microprocessor may communicate with memory dual in-line memory modules (DIMMs). When a programmable device is placed in a processor socket, that programmable device may first be configured using a configuration DIMM and may then communicate with memory DIMMs during normal operation. The configuration DIMM may include multiple options for configuring the programmable device and may also provide additional management functions specifically tailored to the programmable device.

The present invention relates to a single board computer system with an improved memory and layout. The unique layout of the printed circuit board of the present invention allows for different parts to be placed in a back-to-back configuration to minimize the dimensions of the printed circuit board. This includes a high-performance radiation-hardened reconfigurable FPGA, for processing computation-intensive space systems, disposed on both sides of the printed circuit board. Four dual double data rate synchronous dynamic random-access memories (DDR2 SDRAMs) disposed on both the top side and on the bottom side of the printed circuit board reduce an operating voltage of said printed circuit board. A layout stack-up of the printed circuit board includes twenty-two symmetrical layers including ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer.

There is provided a semiconductor apparatus including a memory controller; a CPU; a high-speed communication controller; a memory operation terminal group that includes a plurality of memory operation terminals for inputting a first signal propagating between an external memory group and the memory controller; a high-speed communication terminal group that includes a plurality of high-speed communication terminals for inputting a second signal to the high-speed communication controller; an inspection terminal group that includes a plurality of inspection terminals for acquiring information from the CPU and performing debugging; and a terminal mounting surface at which the memory operation terminal group, the high-speed communication terminal group, and the inspection terminal group are provided, in which at the terminal mounting surface, a first inspection terminal among the plurality of inspection terminals is located between the memory operation terminal group and the high-speed communication terminal group.

There is provided a semiconductor apparatus including a first high-speed communication controller and a second high-speed communication controller that perform high-speed communication; a first high-speed communication terminal group that includes a first high-speed communication terminal for inputting a first signal; a second high-speed communication terminal group that includes a second high-speed communication terminal for inputting a second signal; and a terminal mounting surface, in which the terminal mounting surface includes a first side and a second side, a shortest distance from the first high-speed communication terminal group to the first side is shorter than a shortest distance from the second high-speed communication terminal group to the first side, and a shortest distance from the second high-speed communication terminal group to the second side is shorter than a shortest distance from the first high-speed communication terminal group to the second side.

There is provided a semiconductor apparatus including: a memory operation terminal for inputting a first signal; a high-speed communication terminal for inputting a second signal to a high-speed communication controller; an inspection terminal for performing debugging; and a terminal mounting surface at which a plurality of coupling terminals including the memory operation terminal, the high-speed communication terminal, and the inspection terminal are provided, in which the terminal mounting surface includes a first side, a second side, a third side, and a fourth side, the plurality of coupling terminals include a first terminal row located adjacent to the third side and arranged from the first side toward the second side; the first terminal row includes a first inspection terminal among the plurality of inspection terminals, and the first inspection terminal is located closest to the first side in the first terminal row.