Patent classifications
H05K2201/10378
HIGH PERFORMANCE INTERPOSER AND CHIP SOCKET
An interposer configured for connecting offset arrays of signal pads on parallel surfaces. Contacts of the interposer have mating portions with multiple beams. One of the beams makes contact with a pad on a first of the surfaces and is deflected when the surfaces are pressed together with the interposer between them. A second of the beams is positioned so that the first beam presses into that second beam as the first beam deflects. The second beam may contact a central location on the first beam. An electrical path through the contact from a pad on the first surface to a pad on the second surface may be shorter when the first beam is pressed into the second beam than through the first beam alone. A shorter path may improve signal integrity. Moreover, the spring force of the contact may be set by the second beam.
ELECTRONIC DEVICE INCLUDING PRINTED CIRCUIT BOARD STRUCTURE INCLUDING THERMAL INTERFACE MATERIAL
An electronic device includes a printed circuit board (“PCB”) structure which accommodates a thermal interface material (“TIM”). The PCB structure includes a base plate, a first component on the base plate, a second component on the base plate and apart from the first component, an interposer connected to the base plate and surrounding the first component and the second component, a cover plate connected to the interposer and covering the first component and the second component, and an accommodation part which is between the base plate and a heat conduction plate and accommodates the TIM.
Direct current blocking capacitors and method of attaching an IC package to a PCB
A method of attaching an integrated circuit (IC) package to a printed circuit board (PCB) with a set of direct current (DC) blocking capacitors includes: applying a conductive attachment material to a first set of attachment pads located on a first planar surface of the IC package; aligning the set of DC blocking capacitors in accordance with corresponding positions of the first set of attachment pads; attaching the set of DC blocking capacitors to the IC package by: positioning the aligned set of DC blocking capacitors so that a first surface of a first DC blocking capacitor of the set of DC blocking capacitors is adjacent to a corresponding attachment pad of the first set of attachment pads; and connecting the conductive attachment material to the IC package and to the first surface of the first DC blocking capacitor to create an IC package assembly.
Substrate layered structure and interposer block
A substrate layered structure including a first circuit board; a second circuit board overlapping the first circuit board; and interposer blocks interposed between the first circuit board and the second circuit board and spaced apart from each other. Further, each corresponding interposer block includes a dielectric block body; a plurality of signal via holes passing through the dielectric block body and transferring signals between the first circuit board and the second circuit board; and a plurality of signal pads arranged at first ends of the signal via holes and connected to the first circuit board and arranged at second ends of the signal via holes and connected to the second circuit board.
TRACE ANYWHERE INTERCONNECT
The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side
WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE
A wiring substrate includes a first wiring layer, an insulative resin first insulation layer covering the first wiring layer, and a second wiring layer located on an upper surface of the first insulation layer. A via wiring layer, which extends through the first insulation layer to connect the first and second wiring layers, includes an upper end surface connected to the second wiring layer and flush with the upper surface of the first insulation layer. The second wiring layer has a higher wiring density than the first wiring layer. The first insulation layer includes a first resin layer and a second resin layer located on an upper surface of the first resin layer and having a lower filler content rate than the first resin layer. The upper surface of the first resin layer is a curved surface upwardly curved toward the upper end surface of the via wiring layer.
Package substrate inductor having thermal interconnect structures
Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein a surface of the inductor is substantially coplanar with a surface of the substrate. One or more thermal interconnect structures are on the surface of the inductor. A conductive feature is embedded within a board, where a surface of the conductive feature is substantially coplanar with a surface of the board. One or more thermal interconnect structures are on the surface of the conductive feature of the board, where the thermal interconnect structures provide a thermal pathway for cooling for the inductor.
Substrate connection member comprising substrate having opening part, which encompasses region in which through wire is formed, and conductive member formed on side surface of opening part, and electronic device comprising same
A substrate connection member according to various embodiments of the present invention can comprise a printed circuit board which has a plurality of layers that are stacked and which comprises a front surface, a rear surface, and a side surface encompassing the front surface and the rear surface. The printed circuit board can comprise: an opening part which encompasses a partial region of the printed circuit board and which is penetratingly formed from the front surface to the rear surface; at least one bridge connected between the partial region and the printed circuit board by crossing at least a portion of the opening part; and at least one through-hole wire formed in the partial region from the front surface to the rear surface, wherein the inner surface of the opening part and the side surface of the bridge can be formed from a conductive member. Other various embodiments, in addition to the embodiments disclosed in the present invention, are possible.
POWER CONVERTER ASSEMBLY
A power converter assembly includes an interposer; an integrated circuit, such as a power management integrated circuit, arranged in a cavity or pocket of the interposer or monolithically integrated in the interposer; one or more electrical components stacked on a top side of the interposer; and one or more vias arranged in the interposer forming electrical connections in the interposer, wherein the integrated circuit and the electrical components are configured to perform a power conversion of an input voltage to an output voltage.
Socket loading element and associated techniques and configurations
Embodiments of the present disclosure are directed towards a socket loading element and associated techniques and configurations. In one embodiment, an apparatus may include a loading element configured to transfer a compressive load from a heat spreader to a socket assembly, wherein the loading element is configured to form a perimeter around a die when the loading element is coupled with an interposer disposed between the die and the socket assembly and wherein the loading element includes an opening configured to accommodate the die. Other embodiments may be described and/or claimed.