A method for producing a glass substrate with through glass vias according to the present invention includes: irradiating a glass substrate (10) with a laser beam to form a modified portion; forming a first conductive portion (20a) on a first principal surface of the glass substrate (10), the first conductive portion (20a) being positioned in correspondence with the modified portion (12); and forming a through hole (14) in the glass substrate (10) after formation of the first conductive portion by etching at least the modified portion (12) using an etchant. This method allows easy handling of a glass substrate during formation of a conductive portion such as a circuit on the glass substrate, and is also capable of forming a through hole in the glass substrate relatively quickly while preventing damage to the conductive portion such as a circuit formed on the glass substrate.

An electronic system and associated methods are disclosed. In one example, the electronic system includes a processor package including at least one processor integrated circuit (IC); an interposer including electrically conductive interposer interconnect; a first liquid metal well array including multiple liquid metal wells arranged between the processor package and the interposer, wherein the first liquid metal well array is attached to a surface of the processor package and attached to a first surface of the interposer and the interposer interconnect; a printed circuit board (PCB) attached to a second surface of the interposer and the interposer interconnect; a second liquid metal well array including a first surface attached to the first surface of the interposer and the interposer interconnect; and a first companion component package attached to a second surface of the second liquid metal well array.

An electronic system and associated methods are disclosed. In one example, the electronic system includes an interposer including electrically conductive interposer interconnect, a first interposer surface, and a second interposer surface; a processor package including at least one processor integrated circuit (IC), the processor package attached to the first interposer surface and electrically connected to the interposer interconnect; a first liquid metal well array including multiple liquid metal wells attached to a second interposer surface and the interposer interconnect; a second liquid metal well array including a first array surface attached to the first interposer surface and the interposer interconnect; and a packaged companion IC to the processor IC attached to a second array surface of the second liquid metal well array.

Shielded and packaged electronic devices, electronic assemblies, and methods are disclosed herein. The shielded and packaged electronic devices include a packaged electronic device with a package surface and a plurality of electrically conductive package pads arranged on the package surface, a shielding dielectric layer extending in contact with the package surface and having a shielding layer surface and a plurality of openings that extends between the shielding layer surface and the plurality of electrically conductive package pads, and a plurality of electrical conductors that extends from the plurality of electrically conductive package pads and projects from the shielding layer surface. The electronic assemblies include a printed circuit board with a board surface and a plurality of electrically conductive board pads arranged on the board surface, the shielded and packaged electronic device, and an underfill dielectric layer. The methods include methods of manufacturing the electronic assemblies.

An embodiment of the invention may include a method, and resulting structure, of forming a semiconductor structure. The method may include forming a component hole from a first surface to a second surface of a base layer. The method may include placing an electrical component in the component hole. The electrical component has a conductive structure on both ends of the electrical component. The electrical component is substantially parallel to the first surface. The method may include forming a laminate layer on the first surface of the base layer, the second surface of the base layer, and between the base layer and the electrical component. The method may include creating a pair of via holes, where the pair of holes align with the conductive structures on both ends of the electrical component. The method may include forming a conductive via in the pair of via holes.

Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielectric layer that intercalates a first metal layer of the first metal layers and a second metal layer of the second metal layers. Such layers can be assembled in a nearly concentric arrangement, where the dielectric layer abuts the first metal layer and the second metal layer abuts the dielectric layer. In addition, the capacitive interconnect can include a first electrode electrically coupled to at least one of the first metal layers, and a second electrode electrically coupled to at least one of the second metal layers, the second electrode assembled opposite to the first electrode. The first electrode and the second electrode can include respective solder tops. The capacitive interconnects can be utilized in a semiconductor package, providing a compact assembly that can reduce the utilization of real estate in a board substrate onto which the semiconductor package is mounted.

Apparatus having at least one breakout structure are provided. In one example, an apparatus includes a dielectric layer, first and second contact pads, and first and second vias. The first and second contact pads are disposed on the dielectric layer. The first via is disposed through the dielectric layer and coupled to the first contact pad. The first via is offset from the first contact pad in a first direction. The second contact pad is immediately adjacent the first via. The second via is disposed through the dielectric layer immediately adjacent the first contact pad and coupled to the second contact pad. The second via is offset from the second contact pad in a second direction that is opposite of the first direction. The first and the second contact pads define a first differential pair of contact pads that is configured to transmit a first differential pair of signals.

Apparatuses, systems and methods associated with electrical fast transient tolerant input/output (I/O) communication (e.g., universal serial bus (USB)) design are disclosed herein. In embodiments, an apparatus to mount an integrated circuit (IC) package, may include a printed circuit board (PCB), a plurality of pogo pins, and a mounting mechanism. The plurality of pogo pins may be mounted to electrical contacts of the PCB, the plurality of pogo pins may be coupled to the electrical contacts at first ends of the plurality of pogo pins and may be to couple to the IC package at second ends of the plurality of pogo pins. The mounting mechanism may position the IC package on the second ends of the plurality of pogo pins. Other embodiments may be described and/or claimed.

A reflowable grid array (RGA) interposer includes first connection pads on a first surface of a body and second connection pads on a second surface of the body. Heating elements within the body are adjacent to the second connection pads. First interconnects within the body connect some of the second connection pads to the first connection pads. Second interconnects within the body connect pairs of the second connection pads. A motherboard assembly includes first and second components (e.g., CPU with co-processor and/or memory) and the RGA interposer. The first connection pads are in contact with motherboard contacts. The second connection pads are in contact with the first and second components. The first component passes signals directly to the motherboard by the first interconnects. The second component passes signals directly to the first component by the second interconnects but does not pass signals directly to the motherboard by the first interconnects.

An interposer for a processor includes: an electrically insulating material having a first main side and a second main side opposite the first main side; an electrical interface for a processor substrate at the first main side of the electrically insulating material; and a power device module embedded in the electrically insulating material and configured to convert a voltage provided at the second main side of the electrically insulating material to a lower voltage. The power device module has at least one contact configured to receive the voltage provided at the second main side of the electrically insulating material. Distribution circuitry embedded in the electrically insulating material is configured to carry the lower voltage provided by the power device module to the first main side of the electrically insulating material.