An electronic assembly for use in space missions that includes a PCB and one or more multi-pin CGA devices coupled to the PCB. The PCB has one or more via-in-pad features and each via-in-pad feature comprises a land pad configured to couple a pin of the one or more multi-pin CGA devices to the via. The PCB also includes a plurality of layers arranged symmetrically in a two-halves configuration above and below a central plane of the PCB.

The protective housing can cover at least one component on the circuit board; the interior of the cover has several protrusions that are built, so that at least one part is displaced by raising the protective housing on at least one component, so that it is in contact with the exterior contour of the component and fastens it. Moreover, a circuit board is provided with at least one protective housing.

A chip electronic component includes a multilayer ceramic capacitor and spacers. The multilayer ceramic capacitor includes a multilayer body including inner electrode layers and dielectric layers that are alternately arranged, and outer electrodes. The multilayer body includes capacitor principal surfaces opposite to each other in a lamination direction, capacitor side surfaces opposite to each other in a width direction, and capacitor end surfaces opposite to each other in a length direction. Outer electrodes are provided on respective ones of capacitor end surfaces. The spacers are provided at both ends of one of the capacitor principal surfaces adjacent to a mounting board for the multilayer ceramic capacitor. Each spacer includes spacer principal surfaces opposite to each other in the lamination direction. At least one recess is provided in a surface of one of the spacer principal surfaces adjacent to the mounting board.

Embodiments disclosed herein include passive electrical components with thickness modifications in order to improve embedding processes. In an embodiment, such an apparatus comprises a substrate with a first width, where the substrate comprises a first surface, a second surface opposite from the first surface, and sidewall surfaces coupling the first surface to the second surface. In an embodiment, a layer with a second width that is greater than the first width contacts the substrate and covers the sidewall surfaces and the first surface of the substrate.