A method for manufacturing a circuit board with a small size a communication unit comprising a radio frequency (RF) component, an antenna, and an encapsulation layer. The RF component is embedded in the encapsulation layer, the antenna is positioned on the encapsulation layer and electrically connected to the RF component. A rigid substrate is formed on a flexible substrate, and a receiving groove is defined in the rigid substrate to expose the flexible substrate. The communication unit is in the receiving groove, thus causing connection between the RF component and the flexible substrate, thereby the circuit board is formed.

A mini smart card and a method of manufacturing the mini smart card are introduced. The method includes disposing bilayered print layers on a top side and a bottom side of a circuit layer, respectively; performing a heat-compression treatment and then a printing treatment on the circuit layer and the bilayered print layers; removing surface layers from the bilayered print layers; and disposing transparent protective layers on the bilayered print layers, respectively. The bilayered print layers are prevented from deforming under the heat generated during the printing treatment. Removal of the surface layers from the bilayered print layers effectively reduces the thickness of the mini smart card.

The disclosure describes a soft-matter electronic device having micron-scale features, and methods to fabricate the electronic device. In some embodiments, the device comprises an elastomer mold having microchannels, which are filled with an eutectic alloy to create an electrically conductive element. The microchannels are sealed with a polymer to prevent the alloy from escaping the microchannels. In some embodiments, the alloy is drawn into the microchannels using a micro-transfer printing technique. Additionally, the molds can be created using soft-lithography or other fabrication techniques. The method described herein allows creation of micron-scale circuit features with a line width and spacing that is an order-of-magnitude smaller than those previously demonstrated.

A copper clad laminate and a method to manufacture the same are provided. In one general aspect, a copper clad laminate include a first copper clad layer on a first surface of an insulating layer, and a second copper clad layer on a second surface of the insulating layer. The second copper clad layer includes polymer resin layer, a second copper layer, and a carrier foil layer.

A lamination circuit board structure lamination circuit board structure includes a printed circuit board substrate including conductive wiring traces on at least a first wiring face, a prepreg layer formed over the first wiring face, and a patch having an area smaller than 1,000 mm.sup.2. The patch includes conductive wiring traces formed on a wiring face and is laminated to the printed circuit board substrate over the prepreg layer, oriented with the wiring face in contact with and pressed into the prepreg layer. Portions of the prepreg layer fill interstices between the conductive wiring traces

The present invention provides a surface treated copper foil in which a dropping of the roughening particles from a roughening treatment layer provided on the surface of the copper foil is favorably suppressed and an occurrence of wrinkles or stripes when bonding with an insulating substrate is favorably suppressed. The surface treated copper foil comprises a copper foil, and a roughening treatment layer on at least one surface of the copper foil, wherein an aspect ratio of roughening particles of the roughening treatment layer satisfies one or more of the following items (1) and (2), the aspect ratio being a height of the roughening particles/a thickness of the roughening particles: (1) the aspect ratio of the roughening particles is 3 or less, (2) the aspect ratio of the roughening particles satisfies any one of the following items (2-1) or (2-2): (2-1) the aspect ratio of the roughening particles is 10 or less in the case that the height of the roughening particles is more than 500 nm and 1000 nm or less, (2-2) the aspect ratio of the roughening particles is 15 or less in the case that the height of the roughening particles is 500 nm or less; and a glossiness of a TD of the surface of the side of the roughening treatment layer of the surface treated copper foil is 70% or less.

A power chip package module and a manufacturing method thereof are provided. In the manufacturing method, a temporary carrier having an alignment pattern is provided, in which the temporary carrier includes a base and a peelable adhesive material disposed on the base. Thereafter, a circuit board having an accommodating space passing therethrough is disposed on the temporary carrier according to the alignment pattern. Furthermore, a chip is disposed in the accommodating space with an active surface thereof facing the temporary carrier according to the alignment pattern, in which the chip is fixed on the temporary carrier by the peelable adhesive material. The accommodating space is filled with a molding material to form an initial package structure. The initial package structure is separated from the temporary carrier, and then an electrically and thermally conductive layer is formed on a bottom surface of the chip and is in contact therewith.

A board having an electronic component embedded therein, includes a core layer having a groove with a bottom surface, an electronic component disposed above the bottom surface of the groove and spaced apart from the bottom surface of the groove, and an insulating layer disposed on the core layer and covering at least a portion of the electronic component. The insulating layer is disposed in at least a portion of a space between the bottom surface of the groove and the electronic component.

A circuit board structure includes a circuit layer structure, an electronic component, and a stopper. The circuit layer structure includes a plurality of dielectric layers and circuits in the dielectric layers. The electronic component is disposed in the circuit layer structure; the electronic component includes a chip and a conductive bump; the chip has a first surface and a second surface that are oppositely disposed, and the first surface of the chip contacts one of the dielectric layers; the conductive bump is on the second surface of the chip and is electrically connected to the chip. The stopper is within the circuit layer structure and abuts against the conductive bump. A method for fabricating a circuit board structure is also provided herein.

A method is provided for producing a printed circuit board including at least one conductor element, which extends between connection points in the printed circuit board. In order to increase the productivity of a known method for producing a printed circuit board including at least one conductor element, which extends between connection points in the printed circuit board, the method comprises the following steps: Step A: providing a mold having at least one receptacle for a conductor element; Step B: arranging a conductor element in the receptacle of the mold; Step C: connecting the conductor element arranged in the receptacle of the mold to an electrically conductive sheetlike element at positions of the intended connection points; Step D: embedding the conductor element, which is connected to the electrically conductive sheetlike element, into insulating material; and Step E: working out the connection points from the electrically conductive sheetlike element.