A multilayer printed circuit board includes an inner circuit layer, a first outer circuit layer, a second outer circuit layer, a via, and a layer of high dielectric dissipation solder resist ink. The first outer circuit layer includes a first trace for transmitting a high frequency signal. The inner circuit layer includes a second trace, and is formed between the first outer circuit layer and the second outer circuit layer. The via is formed from the first outer circuit layer to the second outer circuit layer, and is coupled to the first trace and the second trace. The second trace is coupled to the first trace through the via for transmitting the high frequency signal. The layer of high dielectric dissipation solder resist ink is formed on a terminal of the open stub of the via exposed outside of the second outer circuit layer.

A touch screen panel includes a film substrate defined by a touch active area and a non-touch active area and the touch area is arranged outside the touch active area. The touch screen panel includes a plurality of sensing electrodes arranged in the touch active area on an upper surface and a lower surface of the film substrate, and outer lines arranged in the non-touch active area on the upper and the lower surfaces of the film substrate. The outer lines are connected to the sensing electrodes along one of a first direction and a second direction, and the outer lines include a transparent electrode layer and a plating layer on the transparent electrode layer.

The present disclosure provides a method for manufacturing an electrical contact element on a circuit structure, the method comprising depositing a separation layer on a carrier substrate, wherein the carrier substrate comprises the circuit structure, forming a structuring layer with a predefined structure on a basic layer that is arranged between the separation layer and the structuring layer, adding an electrical contact element layer by depositing electrically conductive material on the basic layer via the structuring layer according to the predefined structure, and removing the separation layer, and the structuring layer. Further, the present disclosure provides a respective measurement application device.

A method of manufacturing a wiring substrate according to the present invention includes a step of forming a wiring layer including connection terminals on a first insulating layer; a step of forming a second insulating layer on the wiring layer and on the first insulating layer; a step of forming electrically insulative dummy portions separated from the wiring layer on the first insulating layer through patterning of the second insulating layer; a step of forming a third insulating layer on the wiring layer, on the dummy portions, and on the first insulating layer; and a step of forming openings in the third insulating layer for exposing the connection terminals in such a manner that upper end portions of the connection terminals protrude from the third insulating layer, and lower end portions of the connection terminals are embedded in the third insulating layer.

A printed circuit board (PCB) has multiple layers, where select portions of inner layer circuitry, referred to as inner core circuitry, are exposed from the remaining layers. The PCB having an exposed inner core circuitry is formed using a dummy core plus plating resist process. The select inner core circuitry is part of an inner core. The inner core corresponding to the exposed inner core circuitry forms a semi-flexible PCB portion. The semi-flexible PCB portion is an extension of the remaining adjacent multiple layer PCB. The remaining portion of the multiple layer PCB is rigid. The inner core is common to both the semi-flexible PCB portion and the remaining rigid PCB portion.

A manufacturing method of a substrate structure is provided. The method includes the following steps. Firstly, a conductive carrier is provided. Then, a first metal layer is formed on the conductive carrier. Then, a second metal layer is formed on the first metal layer. Then, a third metal layer is formed on the second metal layer, wherein each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface, the first surface of the third metal layer is connected to the second surface of the second metal layer, the surface area of the first surface of the third metal layer is larger than the surface area of the second surface of the second metal layer, and the first metal layer, the second metal layer and the third metal layer form a conductive structure.

A method of manufacturing a space transformer includes providing a carrier substrate made for a chip package, forming an insulated layer disposed on the carrier substrate, and forming a conductive block. The carrier substrate is formed with elongated first and second wires. The first wire has an elongated contact which is longer than the width of the first wire. The insulated layer is formed with a hole corresponding in position to the elongated contact. The conductive block is formed with an elongated connecting column located in the hole and connected with the elongated contact, and a cylindrical contact pad exposed at the outside of the insulated layer, larger-sized than the elongated connecting column is connected with the elongated connecting column. As a result, the cylindrical contact pad has sufficient area and structural strength for contact with a probe needle.

A method for manufacturing a wiring board includes: disposing a first resist material on a substrate; forming a first resist layer by curing the first resist material; forming a resin layer on a release film; forming a conductor portion on the resin layer; covering the conductor portion by disposing a second resist material on the resin layer; forming a second resist layer by curing the second resist material; bringing the first resist layer into contact with the second resist layer, and thereafter bonding the first resist layer and the second resist layer by thermocompression bonding; and releasing the release film from the resin layer.

An electronic device with an active region comprising a substrate; a first conducting layer, disposed on the substrate, comprising a first pad in the active region; a second conducting layer, disposed on the first conducting layer, comprising a second pad in the active region; a first electronic component, disposed on the first pad, and electronically connected to the first pad; and a second electronic component, disposed on the second pad, and electronically connected to the second pad.