The present invention relates to an electroless plating method, in which electroless plating is performed by contacting a substrate which is patterned with an anti-electroless plating coating with an electroless plating solution, whereby metal is deposited by electroless plating onto portions of the substrate that are not patterned with the anti-electroless plating coating, the anti-electroless plating coating having multiple layers, each of which is obtainable by plasma deposition of a precursor mixture comprising (a) one or more organosilicon compounds, (b) optionally O.sub.2, N.sub.2O, NO.sub.2, H.sub.2, NH.sub.3, N.sub.2, SiF.sup.4 and/or hexafluoropropylene (HFP), and (c) optionally He, Ar and/or Kr.

The embodiments herein relate to a method for selective partitioning of a via in a printed circuit board as to produce an electrically isolating portion between two electrically conducting portions in said via. The method involves the step of prior to drilling the hole for the via, laminating plating resist layers to the printed circuit board at a distance from each other corresponding to a desired length of the electrically isolated portion of the via. After drilling, copper is added to selected portions of the interior of the via in two different processing steps followed by a step of removing undesired copper as to produce the electrically isolating portion.

A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

Provided are a composition for forming a plating layer, which is capable of forming a metal layer having excellent conductivity by means of a plating treatment and is capable of forming a plating layer having excellent adhesiveness to the metal layer, as well as a film having a plating layer precursor layer, a film having a plating layer, a conductive film, and a touch panel, each of which uses the composition for forming a plating layer.

The composition for forming a plating layer according to the present invention includes a non-polymerizable polymer having a group capable of interacting with a metal ion, a polyfunctional monomer having two or more polymerizable functional groups, a monofunctional monomer, and a polymerization initiator.

A method of plating a Printed Circuit Board (PCB) including the steps of: providing a PCB including a solder mask; exposing at least part of the solder mask with UV radiation having an energy density of at least 2000 mJ/cm.sup.2; forming a protected area on the exposed solder mask by printing and curing a radiation curable composition, the radiation curable composition comprising at least one polymerizable compound and at least one photoinitiator; plating an unprotected area of the exposed solder mask; removing at least partially the protected area from the solder mask.