A seeded substrate is first prepared. The seeded substrate includes an insulation substrate having a main surface composed of a first region and a second region other than the first region, and a conductive seed layer provided on the first region. Subsequently, a conductive layer is formed on at least the second region to obtain a first treated substrate. An insulation layer is then formed on the first treated substrate. The seed layer is then exposed. A metal layer is then formed on the surface of the seed layer. Here, a voltage is applied between the anode and the seed layer while a solid electrolyte membrane containing a metal ion-containing solution being disposed between the second treated substrate and the anode, and the solid electrolyte membrane and the seed layer being pressed into contact with each other. Thereafter, the insulation layer and the conductive layer are removed.

A circuit board with high light reflectivity includes an inner wiring base board, a base board with a high light reflectivity, a first insulation layer, a first conductor layer, and a second insulation layer. A first opening in the inner wiring base board receives the base board. The first insulation layer is stacked on a surface of the inner wiring base board and defines a second opening corresponding in position to the first opening and exposing a portion of the base board. The first conductor layer is on a surface of the first insulation layer away from the inner wiring base board and includes connecting pads on the base board. The second insulation layer and the second conductor are stacked in that order on another surface of the inner wiring base board. A method for manufacturing the circuit board is also disclosed.

The present disclosure discloses a circuit board and a manufacturing method thereof. The manufacturing method of the circuit board comprises: forming an electroplated coating on a board body of the circuit board; performing image transfer on the board body; drilling the board body after image transfer to remove a copper layer, adjacent to the two sides of a gold finger, on the circuit board, thereby forming a strip; performing forward and reverse routing towards directions away from each other respectively at the two sides of each gold finger to form a first routing tape and a second routing tape, wherein the first routing tape and the second routing tape are connected to the two ends of the strip respectively; and removing burrs on a surface of the board body through an etching process.

The present publication discloses a method for manufacturing a circuit-board structure. In the method, a conductor layer is made, which comprises a conductor foil and a conductor pattern on the surface of the conductor foil. A component is attached to the conductor layer and the conductor layer is thinned, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern.

A printed wiring board according to as aspect of the present invention includes a base film having insulation properties and a conductive pattern including multiple wiring portions laminated, the conductive pattern running on at least one surface of the base film, wherein each wiring portion includes a first conductive portion and a second conductive portion coating an outer surface of the first conductive portion, wherein an average width of each wiring portion is 10 μm or greater to 50 μm or smaller, and an average thickness of the second conductive portion is 1 μm or greater to smaller than 8.5 μm.

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

Disclosed herein relates to a copper foil having a low roughness property by roughening a matte side, wherein a thickness of the copper foil is from 5 μm to 70 μm, and profilometer-measured mean roughness of the roughened surface of the copper foil is from 0.5 μm to 2.0 μm, and wherein profilometer-measured mean roughness Rz JIS of the roughened matte side of the copper foil is lower than that of a shiny side of the copper foil. The copper foil provided in the present invention has excellent adhesion with a resin and an electrical property while having low roughness through surface roughening.

The present disclosure provides a method for producing a wiring substrate. A seeded substrate is first prepared. The seeded substrate includes an insulation substrate, a conductive undercoat layer having a hydrophilic surface and provided on the insulation substrate, a conductive seed layer provided on a first region of the surface of the undercoat layer, the first region having a predetermined pattern, and a water-repellent layer on the second region of the surface of the undercoat layer, the second region being a region other than the first region. Subsequently, a metal layer is formed on the seed layer. A voltage is applied between the anode and the seed layer while a solid electrolyte membrane being disposed between the seeded substrate and the anode, and the solid electrolyte membrane and the seed layer being pressed into contact with each other. Thereafter, the water-repellent layer and the undercoat layer are etched.

A wiring circuit board includes a metal support layer, a base insulating layer disposed on one side in a thickness direction of the metal support layer, and a conductive layer disposed on one side in the thickness direction of the base insulating layer, and including a first terminal and a ground lead residual portion electrically connected to the first terminal. The base insulating layer has a through hole penetrating in the thickness direction. The ground lead residual portion has an opening continuous so as to surround the through hole.

A printed circuit board includes a first insulating layer; a first wiring layer buried in the first insulating layer, exposed to one surface of the first insulating layer, and including a plurality of first wiring patterns; a second wiring layer including a plurality of second wiring patterns spaced apart from the plurality of first wiring patterns on the one surface of the first insulating layer; and a second insulating layer disposed on the one surface of the first insulating layer and covering the plurality of second wiring layers. At least a portion of the plurality of second wiring patterns on the one surface of the first insulating layer is disposed in regions between adjacent first wiring patterns among the plurality of first wiring patterns.