A printed wiring board production method that forms a base film and a conductive pattern on the base film by an additive method or a subtractive method, includes a plating process that electroplates the conductive pattern on a surface of the base film, wherein the plating process includes a shield plate arranging process that arranges a shield plate between an anode and a printed wiring board substrate that forms a cathode, and a substrate arranging process that arranges the printed wiring board substrate in a plating tank, and wherein a distance between the shield plate and the printed wiring board substrate is 50 mm or greater and 150 mm or less.

A mask for partial plating capable of performing partial electroplating selectively on a prescribed portion on a surface of an electrically isolated metal member provided on an insulated board is provided. Methods for producing an insulated circuit board and using the mask for partial plating are also provided. The mask for partial plating includes an insulated sheet member having an opening corresponding to the portion to be plated, and a structure including a partial region on one surface in the thickness direction of the insulated sheet member being coated with one or plural conductive sheet members attached to the region. The conductive sheet member is adhered to the surface of the insulated sheet member, for example, with an adhesive or an adhesive member. The conductive sheet member may be engaged in a recessed portion formed on the surface of the insulated sheet member.

Provided is a method for manufacturing a circuit board including: (a) preparing a mixture of a metal powder, an anti-sintering agent, and an activator; (b) immersing a dielectric substrate in the mixture; (c) forming a metal-containing layer on the surface of the dielectric substrate by heating the mixture under an inert atmosphere or under a reducing atmosphere; (d) forming a first metal layer on the metal-containing layer by electroless plating and forming a second metal layer thereon by electroplating; and (e) forming a metal pattern on the dielectric substrate, wherein the first metal layer includes Cu, Ni, Co, Au, Pd, or an alloy thereof, the second metal layer includes Cu, Ni, Fe, Co, Cr, Zn, Au, Ag, Pt, Pd, Rh, or an alloy thereof, and the method further includes performing heat treatment at least once after step (c).

The present invention relates to a method for forming a circuit using a seed layer. The method for forming a circuit using a seed layer according to the present invention, may realize a fine pitch, increase the adhesion of the circuit, and prevent the migration phenomenon.

A circuit board has a dielectric core, a foil top surface, and a thin foil bottom surface with a foil backing of sufficient thickness to absorb heat from a laser drilling operation to prevent the penetration of the thin foil bottom surface during laser drilling. A sequence of steps including a laser drilling step, removing the foil backing step, electroless plating step, patterned resist step, electroplating step, resist strip step, tin plate step, and copper etch step are performed, which provide dot vias of fine linewidth and resolution.

A circuit board with high light reflectivity includes an inner wiring base board, a base board with a high light reflectivity, a first insulation layer, a first conductor layer, and a second insulation layer. A first opening in the inner wiring base board receives the base board. The first insulation layer is stacked on a surface of the inner wiring base board and defines a second opening corresponding in position to the first opening and exposing a portion of the base board. The first conductor layer is on a surface of the first insulation layer away from the inner wiring base board and includes connecting pads on the base board. The second insulation layer and the second conductor are stacked in that order on another surface of the inner wiring base board. A method for manufacturing the circuit board is also disclosed.

A flexible printed circuit board includes a base film having an insulating property and a plurality of interconnects laminated to at least one surface side of the base film. The plurality of interconnects includes a first interconnect and a second interconnect in a same plane. An average thickness of the second interconnect being greater than an average thickness of the first interconnect. A ratio of the average thickness of the second interconnect to the average thickness of the first interconnect is greater than or equal to 1.5 and less than or equal to 50. The first interconnect includes a first conductive underlayer and a first plating layer, and the second interconnect includes a second conductive underlayer, a second plating layer, and a third plating layer.

Provided is a display device and an electronic apparatus that prevent the occurrence of failure in the connection between a mounting substrate and an electronic component. The display device includes an interconnection layer provided on a support substrate, a plurality of insulating layers provided above the interconnection layer, an opening provided in parts of the insulating layers, and a metal layer electrically connected to the interconnection layer and filling the opening up to a height below a layer surface of the insulating layer.

Provided is a method for manufacturing a circuit board including: (a) preparing a mixture of a metal powder, an anti-sintering agent, and an activator; (b) immersing a dielectric substrate in the mixture; (c) forming a metal-containing layer on the surface of the dielectric substrate by heating the mixture under an inert atmosphere or under a reducing atmosphere; (d) forming a first metal layer on the metal-containing layer by electroless plating and forming a second metal layer thereon by electroplating; and (e) forming a metal pattern on the dielectric substrate, wherein the first metal layer includes Cu, Ni, Co, Au, Pd, or an alloy thereof, the second metal layer includes Cu, Ni, Fe, Co, Cr, Zn, Au, Ag, Pt, Pd, Rh, or an alloy thereof, and the method further includes performing heat treatment at least once after step (c).

A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.