A mask for partial plating capable of performing partial electroplating selectively on a prescribed portion on a surface of an electrically isolated metal member provided on an insulated board is provided. Methods for producing an insulated circuit board and using the mask for partial plating are also provided. The mask for partial plating includes an insulated sheet member having an opening corresponding to the portion to be plated, and a structure including a partial region on one surface in the thickness direction of the insulated sheet member being coated with one or plural conductive sheet members attached to the region. The conductive sheet member is adhered to the surface of the insulated sheet member, for example, with an adhesive or an adhesive member. The conductive sheet member may be engaged in a recessed portion formed on the surface of the insulated sheet member.

A rigid-flex printed circuit board includes an inner circuit substrate, two adhesive sheet layers formed on the inner circuit substrate, two shielding structures, and two outer circuit layers. The inner circuit substrate is divided into a flexible area, a first and second rigid area. Each shielding structure includes a copper layer, a metal seed layer formed on the copper layer, a flexible dielectric layer formed on the metal seed layer, and a backing adhesive sheet layer formed on the flexible medium layer. The backing adhesive sheet layer is pressed on the adhesive sheet layer and the inner circuit substrate located in the flexible area. Each outer circuit layer is formed on the copper layer, located in the first rigid area and the second rigid area and electrically connected to the inner circuit substrate.

A circuit board includes a substrate, a first circuit layer, a second circuit layer, and a third circuit layer. The substrate includes a base layer, a first metal layer formed on the base layer, and a seed layer formed on the first metal layer. The first circuit layer is located on the substrate and includes the first metal layer and a signal layer formed on a surface of the first metal layer. The second circuit layer is coupled to the first circuit layer and includes the first metal layer, the seed layer, and a connection pillar formed on a surface of the first metal layer and the seed layer. The third circuit layer is coupled to the second circuit layer and includes the seed layer and a coil formed on a surface of the seed layer.

A printed circuit board includes an insulating layer; a metal pad disposed on one side of the insulating layer; a via hole penetrating through the insulating layer to expose at least a portion of the metal pad; and a via filling at least a portion of the via hole, wherein the via comprises a first metal layer and a second metal layer disposed on the first metal layer, and an average size of grains in the first metal layer and an average size of grains in the second metal layer are different from each other.

An elongate, three dimensional, conductive, micro lattice truss structure has parallel layers of resilient strands so that the truss structure maintains structural integrity during end-to-end compression which shortens its uncompressed length. The resiliency of the micro lattice truss structure enables the truss structure to return to substantially its uncompressed length when the compression is removed. The truss structure is adapted to provide a resilient electrical connection between two opposing conductive areas on parallel spaced-apart printed circuit boards when the distal ends of the truss structure engage and are compressed between the two areas.

A copper-clad laminate including at least one of a copper layer having a roughened surface is disclosed. The copper-clad laminate is obtained by roughening at least one surface of a base copper layer so as to have a low profile comprising a copper layer having a thickness of from 5 μm to 70 μm and a resin layer on the copper layer, wherein a peeling strength between the copper layer and the resin layer is more than 0.6 N/mm when the thickness of the copper layer is more than 5 μm, wherein a ten-point mean roughness Sz of the roughened surface is lower than that of the base copper layer.

A method for manufacturing a circuit substrate according to the present disclosure is a method for manufacturing a circuit substrate including an insulation substrate formed with a plurality of via holes passing through a first main surface and a second main surface and a metal with which the via holes are filled, the first and second main surfaces being opposing main surfaces. The method for manufacturing a circuit substrate according to the present disclosure includes: forming, in the insulation substrate, the via hole or a non-through hole opening only on the second main surface; filling the via hole or the non-through hole with the metal; polishing the metal of at least one of the main surfaces to form a step between the metal and the insulation substrate; coating a polished surface of the metal by plating; and polishing the metal on the first main surface and the second main surface.

A printed circuit board includes a core layer having a first through-portion, a coil structure disposed in the first through-portion and comprising a support member, a first coil pattern in a planar spiral form disposed on one surface of the support member, and a body comprising a magnetic substance, wherein the support member and the first coil pattern are accommodated in the body, a first build-up layer covering at least a portion the core layer and disposed in at least a portion of the first through-portion, a first wiring layer disposed on one surface of the first build-up layer, and a first via layer passing through at least a portion of the first build-up layer and connected to the first wiring layer. The first via layer comprises a first wiring via connecting at least a portion of the first wiring layer to the first coil pattern.

An aqueous electrolytic composition and a process for electrodeposition of copper on a dielectric or semiconductor base structure using the aqueous electrolytic composition. The process includes (i) contacting a metalizing substrate comprising a seminal conductive layer on the base structure with an aqueous electrolytic deposition composition; and (ii) supplying electrical current to the electrolytic deposition composition to deposit copper on the substrate. The aqueous electrolytic composition comprises: (a) copper ions; (b) an acid; (c) a suppressor; and (d) a quaternized poly(epihalohydrin) comprising n repeating units corresponding to structure 1N and p repeating units corresponding to structure 1P: ##STR00001##

A method creating a patterned film with cuprous oxide and light comprising the steps of electrodepositing copper from a solution onto a substrate; illuminating selected areas of said deposited copper with light having photon energies above the band gap energy of 2.0 eV to create selected illuminated sections and non-illuminated sections; and stripping non-illuminated sections leaving said illuminated sections on the substrate. An additional step may include galvanically replacing the copper with one or more noble metals.