An aqueous bath for filling a vertical interconnect access or trench of a work piece with nickel or a nickel alloy, the bath comprising a source of nickel ions, and optionally a source of ions of at least one alloying metal, at least one buffering agent, at least one of a dimer of a compound of formula (I) or mixtures thereof ##STR00001## wherein R.sub.1 is a substituted or unsubstituted alkenyl group, R.sub.2 may be present or not, and if present R.sub.2 is a —(CH.sub.2).sub.n—SO.sub.3.sup.− group, wherein n is an integer in the range of 1-6, and wherein one or more of the hydrogens in the group may be replaced by a substituent, preferably hydroxide; and
a method for filling a vertical interconnect access or trench of a work piece with nickel or a nickel alloy with said aqueous bath.

A manufacturing method of copper foil and circuit board assembly for high frequency transmission are provided. Firstly, a raw copper foil having a predetermined surface is produced by an electrolyzing process. Subsequently, a roughened layer including a plurality of copper particles is formed on the predetermined surface by an arsenic-free electrolytic roughening treatment and an arsenic-free electrolytic surface protection treatment. Thereafter, a surface treatment layer is formed on the roughened layer, and the roughened layer is made of a material which includes at least one kind of non-copper metal elements and the concentration of the non-copper metal elements is smaller than 400 ppm. By controlling the concentration of the non-copper elements, the resistance of the copper foil can be reduced.

The disclosure relates to a microcircuit forming method. The microcircuit forming method according to the disclosure comprises: a seed-layer forming step for forming a high-reflectivity seed layer on a substrate material by using a conductive material; a pattern-layer forming step for forming a pattern layer on the seed layer, the pattern layer having a pattern hole arranged thereon to allow the seed layer to be selectively exposed therethrough; a plating step for filling the pattern hole with a conductive material; a pattern-layer removing step for removing the pattern layer; and a seed-layer patterning step for removing a part of the seed layer which does not overlap the conductive material in the plating step, wherein the high-reflectivity seed layer has a specular reflection property.

This disclosure describes systems, methods, and apparatus for multilayer superconducting structures comprising electroplated Rhenium, where the Rhenium operates in a superconducting regime at or above 4.2 K, or above 1.8 K where specific temperatures and times of annealing have occurred. The structure can include at least a first conductive layer applied to a substrate, where the Rhenium layer is electroplated to the first layer. A third layer formed from the same or a different conductor as the first layer can be formed atop the Rhenium layer.

A plating solution including a metal salt, a hydrophilic fullerene, and water, a metal composite material including a hydrophilic fullerene and a method of manufacturing the same, and a wire, a flexible printed circuit (FPC), and an electronic device including the metal composite material.

A circuit board and method of manufacture therefor utilize voltage domain edge plating disposed on at least a portion of one or more edges of a circuit board to electrically couple voltage domain conductive shapes disposed in different conductive layers of the circuit board. By doing so, interconnection of multiple voltage domain conductive shapes in different conductive layers may be facilitated with improved power integrity, while also providing EMI shielding along the edge of the circuit board.

A single-layer redistribution plate functioning as a space translator between a device under testing (“DUT”) and a testing PCB may comprise a hard ceramic plate. A DUT side of the plate may have pads configured to interface with a device under testing. Both sides of the plate may comprise traces, vias, and pads to fan out the DUT pad pattern so that the plate side opposite the DUT side has spatially translated pads configured to interface with the pads on a testing PCB. Fabricating a redistribution plate may comprise calibrating and aligning, laser milling vias, laser milling trenches and pads, copper plating, grinding and polishing, removing residual copper, and coating the copper surfaces.

A printed circuit board (PCB) having an engineered thermal path and a method of manufacturing are disclosed herein. In one aspect, the PCB includes complementary cavities formed on opposite sides of the PCB. The complementary cavities are in a thermal communication and/or an electrical communication to form the engineered thermal path and each cavity is filled with a thermally conductive material to provide a thermal pathway for circuits and components of the PCB. The method of manufacturing may further include drilling and/or milling each cavity, panel plating the cavities and filling the cavities with a suitable filling material.

A circuit board includes a glass substrate having a first surface and a second surface facing away from the first surface; a first coil wiring pattern formed on the first surface and a second coil wiring pattern formed on the second surface, the first and second coil wiring patterns constituting part of a coil; a through hole extending through a predetermined portion of the glass substrate from an end of the first coil wiring pattern to an end of the second coil wiring pattern; a through hole inner conductive surface formed on the inner side of the through hole, the first and second coil wiring patterns and the through hole inner conductive surface constituting the coil wound around a direction perpendicular to an axis of the through hole and to a direction in which the first and second coil wiring patterns extend.

A wiring substrate includes an insulating layer, and a conductor layer including a wiring formed on the insulating layer. The wiring in the conductor layer has a first section and a second section formed such that a wiring width in the second section is smaller than a wiring width in the first section and that a wiring thickness in the second section is larger than a wiring thickness in the first section.