Patent classifications
H05K2203/0766
Method of manufacturing wiring substrate, and wiring substrate
A method of manufacturing a wiring substrate according to the present invention includes a step of forming a wiring layer including connection terminals on a first insulating layer; a step of forming a second insulating layer on the wiring layer and on the first insulating layer; a step of forming electrically insulative dummy portions separated from the wiring layer on the first insulating layer through patterning of the second insulating layer; a step of forming a third insulating layer on the wiring layer, on the dummy portions, and on the first insulating layer; and a step of forming openings in the third insulating layer for exposing the connection terminals in such a manner that upper end portions of the connection terminals protrude from the third insulating layer, and lower end portions of the connection terminals are embedded in the third insulating layer.
PLATING CATALYST AND METHOD
A solution including a precious metal nanoparticle and a polymer polymerized from at least two monomers, (1) a monomer having two or more carboxyl groups or carboxyl acid salt groups and (2) a monomer which has electron-available features. The solution is useful for a catalyst of a process for electroless plating a metal on non-conductive surface.
Substrates having adhesion promotor layers and related methods
Substrate assemblies having adhesion promotor layers and related methods are disclosed. An example apparatus includes a substrate, a dielectric layer, a first copper layer between the substrate and the dielectric layer, and a film between the dielectric layer and the first copper layer. The film including silicon and nitrogen and being substantially free of hydrogen. A via in the dielectric layer is to provide access to the first copper layer. A portion of the first copper layer uncovered in the via, a wall of the via and the portion of the first copper layer to be substantially free of fluorine. A seed copper layer positioned on the dielectric layer. The via wall and the portion of the first copper layer. The seed copper layer and the first copper layer define an undercut at an interface between the seed copper layer and the first copper layer.
Electronic device
Provided is an electronic device. The electronic device includes a substrate and a conductive structure disposed on the substrate, the conductive structure includes a conductive pattern made of a conductive paste and positive ions, the conductive pattern includes conductive particles and a resin, and the positive ions are attached to the resin among the conductive particles. The conductive structure is divided into a plurality of areas in a first direction, and a number of the positive ions in adjacent areas of the conductive structure along the first direction is gradually increased or decreased, in such a manner that the conductive structure is a step resistor.