A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.

Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.

A semiconductor device may include: a first electrode; a second electrode; and a multilayer stack that is interposed between the first electrode and the second electrode and includes a seed layer and a high-k dielectric layer, wherein each of the seed layer and the high-k dielectric layer may have a rocksalt crystal structure, and wherein the high-k dielectric layer may exhibit a dielectric constant (k) of fifty (50) or higher.

The present disclosure relates to a memory device with a vertical field effect transistor (VFET) and a method for preparing the memory device. The memory device includes a capacitor contact disposed in a first semiconductor substrate, and a channel structure disposed over a top surface of the first semiconductor substrate. The memory device also includes a first gate structure disposed on a first sidewall of the channel structure, and a second gate structure disposed on a second sidewall of the channel structure. The second sidewall of the channel structure is opposite to the first sidewall of the channel structure. The memory device further includes a bit line contact disposed over the channel structure. The channel structure is electrically connected to a capacitor and a bit line through the capacitor contact and the bit line contact.

A semiconductor device includes: a bit line; an oxide semiconductor pillar extending vertically from the bit line; a capacitor over the oxide semiconductor pillar; and a word line disposed over a sidewall of the oxide semiconductor pillar, wherein the oxide semiconductor pillar includes: a lower oxide semiconductor interface layer coupled to the bit line; an upper oxide semiconductor interface layer coupled to the capacitor; and an oxide semiconductor channel layer between the lower oxide semiconductor interface layer and the upper oxide semiconductor interface layer.

The present disclosure refers to memory devices and manufacturing methods thereof. In an embodiment, a memory device includes a memory cell array, a first dummy capacitor, a second dummy capacitor, and a third dummy capacitor. The memory cell array includes gate structures formed on a substrate, first active regions adjacent to the gate structures, gate insulating layers disposed between the gate structures and the first active regions, and cell capacitors connected to the first active regions. The first and second dummy capacitors extend in a first direction and in the vertical direction, and are disposed to be adjacent to the memory cell array in a second direction. The third dummy capacitor extends in the second direction and the vertical direction and is disposed to be adjacent to the memory cell array in the first direction. The memory cell array is disposed between the first and second dummy capacitors.

A microelectronic device comprises array regions individually comprising memory cells comprising access devices and storage node device, digit lines coupled to the access devices and extending in a first direction, word lines coupled to the access devices and extending in a second direction orthogonal to the first direction, and control logic devices over and in electrical communication with the memory cells. The microelectronic device further comprises capacitor regions horizontally offset from the array regions in the first direction and having a dimension in the second direction greater than each individual array region in the second direction. The capacitor regions individually comprise additional control logic devices vertically overlying the memory cells, and capacitor structures within horizontal boundaries of the additional control logic devices. Related microelectronic devices, electronic systems, and methods are also described.

A pumping capacitor is provided. The pumping capacitor includes: first, second, third and fourth electrodes that are separately formed on a substrate; a first pumping capacitor group, wherein i first cell capacitors have lower electrodes formed on the first pad electrode and upper electrodes connected to a plate electrode, and (n−i) first cell capacitors have lower electrodes formed on the second pad electrode and upper electrodes connected to the plate electrode; and a second pumping capacitor group, wherein i second cell capacitors have lower electrodes formed on the fourth pad electrode and upper electrodes connected to the plate electrode, and (n−i) second cell capacitors have lower electrodes formed on the third pad electrode and upper electrodes connected to the plate electrode. The first pumping capacitor group and the second pumping capacitor group are connected in series, and the second pad electrode and the third pad electrode are floated.

The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The manufacturing method of a semiconductor structure includes: providing a substrate having bit line contact regions; and forming a first conductive layer and a second conductive layer in each of the bit line contact regions. In the present disclosure, a first conductive layer and a second conductive layer are formed through two deposition processes separately, and a concentration of doped impurities in the first conductive layer is lower than a concentration of doped impurities in the second conductive layer.

A semiconductor device is provided. A semiconductor device includes: a first active pattern spaced apart from a substrate and extending in a first direction; a second active pattern spaced apart further from the substrate than the first active pattern and extending in the first direction; a gate structure on the substrate, the gate structure extending in a second direction crossing the first direction and penetrating the first active pattern and the second active pattern; a first source/drain region on at least one side surface of the gate structure and connected to the first active pattern; a second source/drain region on at least one side surface of the gate structure and connected to the second active pattern; and a buffer layer between the substrate and the first active pattern, the buffer layer containing germanium.