Embodiments of the disclosure provide a semiconductor structure, a method for manufacturing the same and a memory. The semiconductor structure includes a plurality of active pillars and a plurality of conductor lines. Each of the conductor lines includes a plurality of metal layers located in a gap between two adjacent active pillars and a metal compound layer partially surrounding the plurality of active pillars.

A semiconductor structure, a method for manufacturing the same and a memory are provided. The semiconductor structure includes a substrate, multiple first active pillars above the substrate, a memory structure, multiple transistors, and multiple second active pillars. The multiple first active pillars are arranged in an array along a first direction and a second direction. The substrate includes an isolation structure on which the first active pillars are located. The memory structure includes first electrode layers, a dielectric layer and a second electrode layer. The first electrode layer covers a sidewall of the first active pillar, the dielectric layer covers at least surfaces of the first electrode layers, the second electrode layer covers a surface of the dielectric layer. Each of the second active pillars is located above a corresponding one of the first active pillars; a channel structure of each transistor is located in the second active pillar.

Embodiments of the disclosure provide a semiconductor substrate, a method for forming same, and a layout structure. The method includes: providing a semiconductor structure including a first region and a second region arranged in sequence along a second direction, the second region including active structures arranged in an array along a first direction and a third direction, each of the active structure at least including a channel structure, the first direction, the second direction, and the third direction being perpendicular to each other, and the first direction and the second direction being parallel to a surface of the semiconductor substrate; forming a gate structure on a surface of the channel structure; and forming a word line structure extending in the first direction on the first region. The word line structure is connected with the gate structure located on the same layer.

The method for forming the capacitor stack structure includes: providing a substrate on which a plurality of first laminated structures arranged in a first direction and a first isolation structure located between every two adjacent the first laminated structures are formed, and the first laminated structure including first semiconductor layers and second semiconductor layers stacked alternately; forming, in the first laminated structures and the first isolation structures, first trench extending in the first direction, the spacing in a second direction between the adjacent remaining first semiconductor layers is greater than the spacing between the adjacent remaining second semiconductor layers; forming a support structure in the first trench, and removing the first semiconductor layers from the first laminated structure to form a first space; and forming capacitor structures in the first space to form a capacitor stack structure.

A semiconductor structure includes: a substrate; bit lines located in the substrate and including a main body and a plurality of contact portions, the main body extending in a first direction, the contact portions being connected to the main body and extending toward the top surface of the substrate, and the plurality of contact portions being arranged at intervals in the first direction; and transistors located on a top surface of the contact portion, the extension direction of a channel of the transistor being perpendicular to a plane where the substrate is located.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

Embodiments of the disclosure provide a semiconductor structure and a method for forming the same. The method includes: providing a semiconductor substrate including a plurality of active pillars arranged at intervals; etching the active pillar to form an annular groove, in which the annular groove does not expose a top surface and a bottom surface of the active pillar; and forming a first semiconductor layer in the annular groove to form the semiconductor structure; in which a band gap of the first semiconductor layer is smaller than a band gap of the active pillar.

Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a semiconductor device includes a first transistor comprising a first channel region. The first channel region includes one or more first nanostructures formed of a semiconductor material. The semiconductor device includes a second transistor disposed vertically with respect to the first transistor and comprising a second channel region. The second channel region includes one or more second nanostructures formed of a conductive oxide material.

A semiconductor structure and a method for manufacturing a semiconductor structure are provided, which relate to the technical field of semiconductors. The semiconductor structure includes a substrate and a plurality of first conductive layers. The substrate includes a plurality of first trenches extending in a first direction and a plurality of second trenches extending in a second direction. A plurality of active pillars are provided between the plurality of first trenches and the plurality of second trenches. The first direction intersects with the second direction. Each of the plurality of first conductive layers is arranged on each of sidewalls, which are arrayed in the first direction, of a respective one of the plurality of active pillars.

A semiconductor structure includes a substrate and a plurality of word lines located on a top surface of the substrate. Each of the word lines extends in a direction perpendicular to the top surface of the substrate. The plurality of word lines are arranged at intervals along a first direction. Any two adjacent ones of the word lines are arranged in an at least partially staggered manner along the first direction. The first direction is a direction parallel to the top surface of the substrate.