A method used in forming an array of vertical transistors comprises forming laterally-spaced vertical projections that project upwardly from a substrate in a vertical cross-section. The vertical projections individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. First gate insulator material is formed along opposing sidewalls of the channel region in the vertical cross-section. One of (a) or (b) is formed over opposing sidewalls of the first gate insulator material in the vertical cross-section, where (a): conductive gate lines that are horizontally elongated through the vertical cross-section; and (b): sacrificial placeholder gate lines that are horizontally elongated through the vertical cross-section. The one of the (a) or the (b) laterally overlaps the upper source/drain region and the lower source/drain region. The first gate insulator material has a top that is below a top of the channel region and has a bottom that is above a bottom of the channel region. An upper void space is laterally between the one of the (a) or the (b) and both of the upper source/drain region and the channel region. A lower void space is laterally between the one of the (a) or the (b) and both of the lower source/drain region and the channel region. Second gate insulator material is formed in the upper and lower void spaces. Other embodiments, including structure independent of method, are disclosed.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a base; forming bit lines on the base, and forming semiconductor channels on surfaces of the bit lines away from the base, the semiconductor channel including a first doped region, a channel region and a second doped region arranged sequentially; forming a first dielectric layer, the first dielectric layer surrounding sidewalls of the semiconductor channels, and a first gap being provided between parts of the first dielectric layer located on sidewalls of adjacent semiconductor channels on a same bit line; forming a second dielectric layer, the second dielectric layer filling up the first gaps, and a material of the second dielectric layer being different from a material of the first dielectric layer; removing a part of the first dielectric layer to expose sidewalls of the channel regions.

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base; bit lines, located on the base, and a material of the bit line including a metal semiconductor compound; semiconductor channels, each including a first doped region, a channel region and a second doped region arranged in sequence, and the first doped region being in contact with the bit line; a first dielectric layer, covering sidewall surfaces of the first doped regions, and a first interval being provided between parts of the first dielectric layer covering sidewalls of adjacent first doped regions on a same bit line; an insulating layer, covering sidewall surfaces of the channel regions; word lines, covering a sidewall surface of the insulating layer away from the channel regions, and a second interval being provided between adjacent word lines.

Disclosed in the embodiments of the present disclosure are a semiconductor structure and method for manufacturing same, and a memory. The semiconductor structure includes: a plurality of first active columns arranged in an array along a first direction and a second direction, a plurality of first electrodes located in first grooves arranged at intervals, a plurality of first dielectric layers, and a second electrode covering surfaces of the first dielectric layers. The first direction and the second direction are perpendicular to the extension direction of the first active column, and the first direction is intersected with the second direction. Each first electrode covers a side wall of one of the first active columns. Each first groove surrounds a surface of each first active column. Each first dielectric layer covers the side wall of one of the first electrodes and a bottom of a gap between two adjacent first electrodes.

The present disclosure provides a method of manufacturing a semiconductor structure, and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple initial active pillars on the substrate; forming a gate layer between initial active pillars; and forming a first dielectric layer with openings on the gate layer and on the initial active pillars; removing part of the initial active pillar located in each opening to form an active pillar; and removing part of the gate layer to form an isolation trench and a word line, such that two adjacent active pillars in the same row are located on two sides of the isolation trench.

The disclosure provides a semiconductor structure and a method for manufacturing a semiconductor structure, relates to the field of semiconductor manufacturing technologies. The semiconductor structure includes: a substrate, having a bit line groove; a bit line, located in the bit line groove, and extending in a first direction; and a vertical transistor, located on the bit line. The bit line includes a bit line contact structure, and the bit line contact structure is a concave structure and/or a convex structure. The vertical transistor is electrically connected to the bit line by the bit line contact structure.

A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate, multiple active pillars located in the substrate, and multiple word lines. The multiple active pillars are arranged in an array in a first direction and a second direction. The first direction and the second direction are both directions parallel to a top surface of the substrate, and the first direction and the second direction intersect. The multiple word lines are spaced apart in the first direction. Each of the word lines extends in the second direction and continuously surrounds and covers a portion of a side wall of each of the multiple active pillars arranged in the second direction. Any two adjacent word lines are at least partially staggered in a direction perpendicular to the top surface of the substrate.

A transistor comprises semiconductor material that is generally L-shaped or generally mirror L-shaped in at least one straight-line vertical cross-section thereby having an elevationally-extending stem and a base extending horizontally from a lateral side of the stem above a bottom of the stem. The semiconductor material of the stem comprises an upper source/drain region and a channel region there-below. The transistor comprises at least one of (a) and (b), where (a): the semiconductor material of the stem comprises a lower source/drain region below the channel region, and (b): the semiconductor material of the base comprises a lower source/drain region. A gate is operatively laterally adjacent the channel region of the stem. Other embodiments are disclosed, including arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor. Methods are disclosed.

A device structure includes transistors on a first level in a first region and a first plurality of capacitors on a second level, above the first level, where a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor. The device structure further includes a second plurality of capacitors on the second level in a second region adjacent the first region, where individual ones of the second plurality of capacitors include a second electrode, a third electrode and an insulator layer therebetween, where the second electrode of the individual ones of the plurality of capacitors are coupled with a first interconnect on a third level above the second level, and where the third electrode of the individual ones of the plurality of capacitors are coupled with a second interconnect.

A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization level. A first transistor and a laterally separated second transistor are on a same plane above the second interconnect line, where a gate of the first transistor is coupled to the first interconnect line and a gate of the second transistor is coupled to the second interconnect line. A first capacitor is coupled to a first terminal of the first transistor and a second capacitor is coupled to a first terminal of the second transistor. A third interconnect line couples a second terminal of the first transistor with a second terminal of the second transistor.