A method for forming a memory includes: forming a bit line structure and a capacitor contact layer, where the bit line structure includes a bit line, a bit line cap layer and a bit line isolation layer, and the capacitor contact layer covers part of a side wall of the bit line isolation layer; forming a stop layer covering the side wall of the bit line isolation layer; forming a capacitor landing layer covering a top surface of the capacitor contact layer; and etching the bit line isolation layer by using the stop layer as an etch stop layer to form an air gap in the bit line isolation layer. Probability of occurrence of a short circuit between the capacitor landing layer and a bit line is reduced.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base; a plurality of channel pillars perpendicularly provided on the base; a plurality of parallel bit lines, each of the bit lines wrapping lower parts of one column of the channel pillars; and a plurality of parallel word lines, each of the word lines wrapping upper parts of one row of the channel pillars, where the word lines and the bit lines are perpendicular to each other on a same projection plane; an insulating material layer is formed around the channel pillars below the bit lines, between adjacent bit lines, around the channel pillars between the bit lines and the word lines, and between adjacent word lines, separately; and gaps are formed in at least one of the insulating material layers.

The present application discloses a method for fabricating the semiconductor device. The method for fabricating a semiconductor device includes providing a substrate having a first lattice constant and forming a first word line positioned in the substrate and a plurality of stress regions positioned adjacent to lower portions of sidewalls of the first word line. The plurality of stress regions have a second lattice constant, the second lattice constant of the plurality of stress regions is different from the first lattice constant of the substrate.

A method for manufacturing a semiconductor structure includes the following operations. A substrate is provided, and is etched to form first isolation trenches in a cell region and a second isolation trench in a peripheral region. A first isolation dielectric layer is filled in each of the first isolation trenches and an isolation structure is formed in the second isolation trench. A patterned mask layer is formed on surfaces of the cell region and the peripheral region. The substrate and the first isolation dielectric layer are etched based on the patterned mask layer to form the third isolation trenches extending along a second direction. The third and first isolation trenches isolate multiple active pillars. The active pillar includes a first connecting end, a second connecting end and a channel region.

Disclosed are DRAM devices and methods of forming DRAM devices. One non-limiting method may include providing a device, the device including a plurality of angled structures formed from a substrate, a bitline and a dielectric between each of the plurality of angled structures, and a drain disposed along each of the plurality of angled structures. The method may further include providing a plurality of mask structures of a patterned masking layer over the plurality of angled structures, the plurality of mask structures being oriented perpendicular to the plurality of angled structures. The method may further include etching the device at a non-zero angle to form a plurality of pillar structures.

The present application provides a method for fabricating a semiconductor device including providing a substrate, concurrently forming a first conductive line and a bottom contact on the substrate, concurrently forming a first conductive line spacer on a sidewall of the first conductive line and a bottom contact spacer on a sidewall of the bottom contact, forming a first insulating layer over the substrate and concurrently forming an air gap between the first conductive line spacer and the bottom contact spacer.

A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric film extending on the lower electrode along a side surface of the lower electrode that is perpendicular to the substrate, an upper electrode on the capacitor dielectric film, an interface layer including a hydrogen blocking film and a hydrogen bypass film on the upper electrode, the hydrogen blocking film including a conductive material, and a contact plug penetrating the interface layer and electrically connected to the upper electrode.

The present application provides a memory device with an air gap. The memory device includes an active region disposed in a substrate; a word line disposed in the substrate, wherein the word line is intersected with the active region; a contact structure disposed on the substrate, wherein the contact structure is located at a side of the word line, and electrically connected to the active region; a first conductive layer and a second conductive layer disposed over the substrate, wherein the contact structure is covered by the first and second conductive layers; a conductive pillar overlapped with and electrically connected to the contact structure; a landing pad covers and electrically connects to the conductive pillar, wherein a sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad; and a dielectric layer laterally surrounding the conductive pillar and the landing pad.

A stacked memory device includes a plurality of lower word lines extending in a first direction, a bit line positioned over the plurality of the lower word lines and extending in a second direction intersecting with the first direction, and a plurality of upper word lines positioned over the bit line and extending in the first direction. The stacked memory device also includes a plurality of lower memory cells including a lower capacitor and a lower switching element between the lower word lines and the bit line. The stacked memory device further includes a plurality of upper memory cells including an upper capacitor and an upper switching element between the bit line and the upper word lines.

A capacitor structure, a semiconductor memory device including the same, a method for fabricating the same, and a method for fabricating a semiconductor device including the same are provided. The capacitor structure includes a lower electrode, an upper electrode, and a capacitor dielectric film which is interposed between the lower electrode and the upper electrode, wherein the lower electrode includes an electrode film including a first metal element, and a doping oxide film including an oxide of the first metal element between the electrode film and the capacitor dielectric film, and the doping oxide film further includes a second metal element including at least one of Group 5 to Group 11 and Group 15 metal elements, and an impurity element including at least one of silicon (Si), aluminum (Al), zirconium (Zr) and hafnium (Hf).