A semiconductor memory device includes a substrate including a memory cell region, a plurality of capacitor structures arranged in the memory cell region of the substrate and including a plurality of lower electrodes, a capacitor dielectric layer, and an upper electrode, a first support pattern contacting sidewalls of the plurality of lower electrodes of the plurality of capacitor structures to support the plurality of lower electrodes, and a second support pattern located at a higher vertical level than a vertical level of the first support pattern and contacting the sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes. The plurality of lower electrodes have a plurality of recessed electrode portions, respectively, in upper portions of the plurality of lower electrodes.

The present application provides a memory device having a double-sided capacitor. The memory device includes a semiconductor substrate; a capacitor protruding from the semiconductor substrate; a first supporting layer disposed on the semiconductor substrate and surrounding the capacitor; and a second supporting layer disposed above the first supporting layer and surrounding the capacitor, wherein the second supporting layer includes a first opening extending through the second supporting layer and disposed adjacent to the capacitor.

A method of fabricating a semiconductor device, the method including etching a portion of a substrate including a first region and a second region to form a device isolation trench; forming a device isolation layer defining active regions by sequentially stacking a first insulating layer, a second insulating layer, and a third insulating layer on an inner surface of the device isolation trench; forming word lines buried in the substrate of the first region, the word lines extending in a first direction to intersect the active region of the first region, the word lines being spaced apart from each other; forming a first mask layer covering the word lines on the substrate of the first region, the first mask layer exposing the substrate of the second region; forming a channel layer on the substrate of the second region; and forming a gate electrode on the channel layer.

The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method of manufacturing a semiconductor structure includes: forming a first stacked structure, and forming a first target structure in the first stacked structure; and forming a second stacked structure on the first stacked structure, and forming a second target structure in contact with the first target structure in the second stacked structure.

A semiconductor device includes a first device isolation region and a second device isolation region defining a first active region, a second active region, and a third active region in a substrate, a recess region exposing an upper surface of the first active region and upper surfaces of the first and second device isolation regions, and active buffer patterns on the second and third active regions. The first active region is located between the second and third active regions, the first device isolation region is located between the first and second active regions, the second device isolation region is located between the first and third active regions. Upper sidewalls of the second and third active regions are exposed in the recess region.

The stack capacitor structure includes a substrate, first, second, third, and fourth support layers, first, second, and third insulating layers, first, second, and third holes, and a capacitor. The first support layer is disposed over the substrate. The first insulating layer is disposed on the first support layer. The second support layer is disposed on the first insulating layer. The third support layer is disposed on the second support layer. The second insulating layer is disposed on the third support layer. The third insulating layer is disposed on the second insulating layer. The fourth support layer is disposed on the third insulating layer. The first hole penetrates through from the second support layer to the first support layer. The second and third holes penetrate through from the fourth support layer to the third support layer. The capacitor is disposed in the first, second, and third holes.

A method used in forming integrated circuitry comprises forming an array of structures elevationally through a stack comprising first and second materials. The structures project vertically relative to an outermost portion of the first material. Energy is directed onto vertically-projecting portions of the structures and onto the second material in a direction that is angled from vertical and that is along a straight line between immediately-adjacent of the structures to form openings into the second material that are individually between the immediately-adjacent structures along the straight line. Other embodiments, including structure independent of method, are disclosed.

Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.

A nanoscale structure includes an array of pillars over an underlying layer, a separation wall layer including first separation walls formed over sidewalls of the pillars, and a block co-polymer (BCP) layer formed over the separation wall layer and filling gaps between the pillars. The BCP layer is phase-separated to include first domains that provide second separation walls formed over the first separation walls and second domains that are separated from each other by the first domains.

A semiconductor device includes a substrate, a gate feature, a gate spacer, and a dielectric layer. The gate feature is above the substrate and includes a gate electrode. The gate spacer is on a sidewall of the gate feature. The dielectric layer is in contact with the gate spacer and has a larger thickness than the gate electrode.