Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a semiconductor substrate including a first region and a second region, a dummy separation pattern provided on the second region of the semiconductor substrate to have a recessed region at its upper portion, a first electrode provided on the first region of the semiconductor substrate, a dielectric layer covering the first electrode, a second electrode provided on the dielectric layer, and a remaining electrode pattern provided in the recessed region. The second electrode and the remaining electrode pattern may be formed of a same material.

A semiconductor device and method of manufacturing are provided. The semiconductor device includes a substrate; first and second structures spaced apart from each other on the substrate in a first direction, the first structure including a first lower electrode and the second structure including a second lower electrode; a first supporter pattern disposed on the substrate to support the first and second structures, and including a first region that exposes portions of sidewalls of the first and second structures, and a second region that covers a second portion of the sidewalls; and a second supporter pattern disposed on the first supporter pattern to support the first and second structures, the second supporter pattern including a third region, the third region configured to expose portions of the first sidewall and the second sidewall, and a fourth region that covers a portion of the first and second sidewalls.

Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.

Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. A first conductive line of the first series and a first conductive line of the second series are coupled with a first component through a first conductive path. A second conductive line of the first series and a second conductive line of the second series are coupled with a second component through a second conductive path. The first and second conductive lines of the first series extend through first isolation circuitry to the first and second conductive paths, respectively; and the first and second conductive lines of the second series extend through second isolation circuitry to the first and second conductive paths, respectively.

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a semiconductor substrate including a first region and a second region, a dummy separation pattern provided on the second region of the semiconductor substrate to have a recessed region at its upper portion, a first electrode provided on the first region of the semiconductor substrate, a dielectric layer covering the first electrode, a second electrode provided on the dielectric layer, and a remaining electrode pattern provided in the recessed region. The second electrode and the remaining electrode pattern may be formed of a same material.

Memory devices include a first dielectric layer disposed on a substrate. Memory devices include a pair of contacts and a dielectric portion disposed in an opening of the first dielectric layer. The pair of contacts are separated from each other by the dielectric portion. Each contact includes a first conductive portion disposed on the substrate, a second conductive portion disposed over the first conductive portion and a lining layer disposed between the first conductive portion and the second conductive portion and on a sidewall of the opening. The second conductive portion has a sidewall that is in contact with the dielectric portion and the lining layer is not located thereon. The second conductive portion has a corner in connection with the sidewall and a top surface of the second conductive portion, and a protection portion is disposed on the corner.

A method for fabricating a semiconductor device is provided. The method includes the actions of: providing a substrate comprising a preliminary pattern formed thereon; forming an opening through the preliminary pattern to expose a conductive portion in the substrate; forming a dielectric layer on a sidewall of the opening; performing a dry etching process to form a hole in the conductive portion; removing the dielectric layer; and depositing a conductive pattern over the sidewall of the opening and in the hole.

A method for fabricating a semiconductor device is provided. The method includes the actions of: providing a substrate comprising a preliminary pattern formed thereon; forming an opening through the preliminary pattern to expose a conductive portion in the substrate; forming a spacer on a sidewall of the opening; performing an wet etching process to form a hole in the conductive portion; removing the spacer; and depositing a conductive pattern over the sidewall of the opening and a surface of the hole.

A method of fabricating a semiconductor device includes providing a substrate including a pair of first regions and a second region therebetween, forming first patterns on the respective first regions to at least partially define a stepwise portion at the second region, and forming a dummy pattern that at least partially fills the stepwise portion. The dummy pattern may be an electrically floating structure. The dummy pattern may be formed as part of forming second patterns on the respective first regions, and the dummy pattern and the second patterns may include substantially common materials. Because the dummy pattern at least partially fills the stepwise portion at the second region, the material layer covering the second patterns and the dummy pattern may omit a corresponding stepwise portion.