A semiconductor structure and a method of forming it are disclosed by the present application. Deep trench capacitors are formed in a substrate, and fin contacts formed by upper portions of inner electrodes in the deep trench capacitors are connected to fins on a surface of the substrate. At least one of word lines formed on the substrate pass over and are separated by a word line isolation layer from the inner electrodes. The word line isolation layer covers portions of the inner electrodes between a buried oxide layer and the fin contacts, while the fins are exposed therefrom.

A semiconductor memory device and a method for fabricating the device are disclosed. In the semiconductor memory device, a doped epitaxial silicon layer epitaxially grown on a surface of a silicon layer within a trench electrically connects a transistor to a trench capacitor.

A memory device and a method for manufacturing a memory device are provided. The memory device includes: a substrate, and a plurality of first capacitors embedded in the substrate; a plurality of first vertical transistors and a plurality of second vertical transistors, in which the plurality of first vertical transistors and the plurality of second vertical transistors are arranged on the substrate, and in which each of the plurality of first vertical transistors is electrically connected to a respective one of the plurality of first capacitors; and a plurality of second capacitors arranged on the plurality of first vertical transistors and the plurality of second vertical transistors, in which each of the plurality of second capacitors is electrically connected to a respective one of the plurality of second vertical transistors.

The disclosed technology relates to dynamic random access memory (DRAM) devices. The disclosed technology provides an integrated DRAM device including a DRAM and a logic circuit configured to control the DRAM. In one aspect, a DRAM device includes a plurality of stacked transistors arranged in a first region of the DRAM device, the stacked transistors being disposed one over another along a stacking direction, and a storage capacitor arranged in a second region of the DRAM device. The first region is positioned above the second region along the stacking direction. One of the plurality of stacked transistors is connected to the storage capacitor to form a DRAM cell of the DRAM, and remaining one or ones of the plurality of stacked transistors forms at least a portion of the logic circuit.

Embodiments of this disclosure provide a semiconductor structure, including a metal layer disposed on a substrate, a first dielectric layer disposed on the metal layer, a second dielectric layer disposed on the first dielectric layer, a first insulating layer disposed on the second dielectric layer, a plurality of capacitors disposed on the metal layer in the first dielectric layer and the second dielectric layer, and a contact disposed on the metal layer in the first dielectric layer, the second dielectric layer and the first insulating layer. A top surface of the contact and a top surface of the first insulating layer are coplanar. Additionally, a method of manufacturing a semiconductor structure is also disclosed in this disclosure.

A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate, an upper structure, a vertical transistor an electrical pad. The upper structure is disposed on the substrate and defines a hole. The vertical transistor is disposed in the hole. The electrical pad is disposed in the hole and on the vertical transistor. A top surface of the electrical pad is substantially aligned with a topmost surface of the upper structure.

A semiconductor structure and a method of forming it are disclosed by the present application. Deep trench capacitors are formed in a substrate, and fin contacts formed by upper portions of inner electrodes in the deep trench capacitors are connected to fins on a surface of the substrate. At least one of word lines formed on the substrate pass over and are separated by a word line isolation layer from the inner electrodes. The word line isolation layer covers portions of the inner electrodes between a buried oxide layer and the fin contacts, while the fins are exposed therefrom.

A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate, an upper structure, a vertical transistor an electrical pad. The upper structure is disposed on the substrate and defines a hole. The vertical transistor is disposed in the hole. The electrical pad is disposed in the hole and on the vertical transistor. A top surface of the electrical pad is substantially aligned with a topmost surface of the upper structure.

A method of making a semiconductor device includes forming a first transistor on a substrate, wherein forming the first transistor comprises forming a first source/drain electrode in the substrate. The method further includes forming a second transistor on the substrate, wherein forming the second transistor comprises forming a second source/drain electrode. The method further includes forming an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode, and the insulating layer extends above a top-most surface of the substrate.