A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.

A semiconductor device includes an insulating base including a trench, a transistor including a gate electrode and vertical channel in the trench, and a source electrode in the insulating base outside the trench, an isolation layer on the gate electrode in the trench, and a capacitor including a trench capacitor portion that is on the isolation layer in the trench, and a stacked capacitor portion that is coupled to the source electrode of the transistor outside the trench.

A semiconductor device includes an insulating base including a trench, a transistor including a gate electrode and vertical channel in the trench, and a source electrode in the insulating base outside the trench, an isolation layer on the gate electrode in the trench, and a capacitor including a trench capacitor portion that is on the isolation layer in the trench, and a stacked capacitor portion that is coupled to the source electrode of the transistor outside the trench.

To provide a highly integrated semiconductor memory device. To provide a semiconductor memory device which can hold stored data even when power is not supplied. To provide a semiconductor memory device which has a large number of write cycles. The degree of integration of a memory cell array is increased by forming a memory cell including two transistors and one capacitor which are arranged three-dimensionally. The electric charge accumulated in the capacitor is prevented from being leaking by forming a transistor for controlling the amount of electric charge of the capacitor in the memory cell using a wide-gap semiconductor having a wider band gap than silicon. Accordingly, a semiconductor memory device which can hold stored data even when power is not supplied can be provided.

The semiconductor storage device includes a lower electrode that are vertically extended from a semiconductor substrate, a beam including a first portion extending in a horizontal direction to support the lower electrode and a second portion that is vertically extended along the exterior wall of the electrode from the first portion.

Provided is a semiconductor memory device. The semiconductor memory device includes a substrate, a channel region on the substrate, first and second source/drain regions electrically connected to the channel region, a gate electrode that extends in a first direction and is on the channel region, a conductive line that extends in a second direction intersecting the first direction and is electrically connected to the second source/drain region, and a capacitor structure electrically connected to the first source/drain region on the substrate. The capacitor structure may include a plurality of first electrodes stacked and spaced apart from each other in a third direction perpendicular to an upper surface of the substrate, a plurality of trenches extending into the plurality of first electrodes, a capacitor dielectric film that extends along side walls of each of the plurality of trenches, and a plurality of second electrodes in the plurality of trenches, respectively.

A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.

Provided are a capacitor, an electronic device including the same, and a method of manufacturing the same, the capacitor including a first thin-film electrode layer; a second thin-film electrode layer; a dielectric layer between the first thin-film electrode layer and the second thin-film electrode layer; and an interlayer between the dielectric and at least one of the first thin-film electrode layer or the second thin-film electrode layer, the interlayer including a same crystal structure type as and a different composition from at least one of the first thin film electrode layer, the second thin film electrode layer, or the dielectric layer, the interlayer including at least one of a anionized layer or a neutral layer.

One aspect of the present disclosure pertains to a memory device. The memory device includes a semiconductor feature made of a compound semiconductor material. The semiconductor features includes a first portion as a first source/drain (S/D) feature, a second portion as a channel, and a third portion as a second S/D feature. The first portion is above the second portion and the second portion is above the third portion, and the second portion vertically extends from the first portion to the third portion. The memory device includes a gate structure horizontally wrapping around the second portion and a capacitor structure in direct contact with and wrapping around the semiconductor feature.

Provided are a capacitor, an electronic device including the same, and a method of manufacturing the same, the capacitor including a first thin-film electrode layer; a second thin-film electrode layer; a dielectric layer between the first thin-film electrode layer and the second thin-film electrode layer; and an interlayer between the dielectric and at least one of the first thin-film electrode layer or the second thin-film electrode layer, the interlayer including a same crystal structure type as and a different composition from at least one of the first thin film electrode layer, the second thin film electrode layer, or the dielectric layer, the interlayer including at least one of a anionized layer or a neutral layer.