Memory devices including vertical transistors and methods of forming such memory devices are disclosed. An example memory device includes a substrate, a BL in the substrate, a channel region over a portion of the BL, a second region over the channel region, an insulator wrapped around at least a portion of the channel region, and a WL. The BL also operates as one of a source region and a drain region of the transistor. The second region is the other one of the source region and the drain region. The WL wraps around at least a portion of the insulator and is separated from the channel region by the insulator. In some embodiments, the BL is formed in a trench in the substrate. An aspect ratio of the BL is in a range from 0.5 to 10. The BL may have a higher conductivity than the channel region.

A method of fabricating a semiconductor structure includes depositing a first dielectric layer on a substrate; depositing a second dielectric layer on the first dielectric layer; forming a capacitor in the first dielectric layer and the second dielectric layer; depositing a first insulating layer on the second dielectric layer and the capacitor; forming a word line structure on the first insulating layer; depositing a second insulating layer on the word line structure; forming a channel hole in the second insulating layer, the word line structure, and the first insulating layer, wherein the channel hole includes a first section with a trumpet shape opening and a second section below the first section; forming a vertical channel in the second section of the channel hole; and forming a landing pad in the first section of the channel hole. A semiconductor structure is also disclosed.