A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, contact structures coupled to the digit lines, word lines coupled to the memory cells, additional contact structures coupled to the word lines, and isolation material surrounding the contact structures and the additional contact structures and overlying the memory cells. An additional microelectronic device structure assembly is formed and comprises control logic devices, further contact structures coupled to the control logic devices, and additional isolation material surrounding the further contact structures and overlying the control logic devices. The additional microelectronic device structure assembly is attached to the microelectronic device structure assembly by bonding the additional isolation material to the isolation material and by bonding the further contact structures to the contact structures and the additional contact structures. Microelectronic devices and electronic systems are also described.

A method for fabricating a semiconductor device includes forming a line structure including a first contact plug on a semiconductor substrate and a conductive line on the first contact plug, forming a low-k layer having a first low-k, which covers a top surface and side walls of the line structure, performing a converting process on the low-k layer to form a non-converting portion adjacent to side walls of the first contact plug and maintains the first low-k and a converting portion adjacent to side walls of the conductive line and having a second low-k that is lower than the first low-k, and forming a second contact plug which is adjacent to the first contact plug with the non-converting portion therebetween while being adjacent to the conductive line with the converting portion therebetween.

Described herein are three-dimensional memory arrays that include multiple layers of memory cells. The layers are stacked and bonded to each other at bonding interfaces. The layers are formed on a support structure, such as a semiconductor wafer, that is grinded down before the layers are bonded. Vias extend through multiple layers of memory cells, including through the support structures and bonding interfaces. Thinning the support structure enables a tighter via pitch, which reduces the portion of the footprint used for vias. The memory cells may include three-dimensional transistors with a recessed gate and extended channel length.

The present disclosure relates to a semiconductor memory device and a fabricating method thereof, which includes a substrate and a plurality of word lines. The substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation and the active structure includes a first active area and a second active area. The first active area includes a plurality of active area units being parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area, to surround all of the active area units. The word lines are disposed in the substrate to intersect the active area units and the shallow trench isolation. The word lines includes first word lines arranged by a first pitch and second word lines arranged by a second pitch, and the second pitch is greater than the first pitch.

A contact forming method may include providing a semiconductor substrate including a silicon oxide film to an interior of a chamber, subjecting a surface of the silicon oxide film to plasma nitrification treatment, supplying a source gas including TiCl.sub.4 and H.sub.2 onto the silicon oxide film subjected to the plasma nitrification treatment, and forming a barrier layer by igniting a plasma using the source gas.

A method for fabricating a semiconductor device includes: forming a first conductive structure over a substrate; forming a multi-layer spacer including a non-conformal sacrificial spacer on both sidewalls of the first conductive structure; forming a second conductive structure adjacent to the first conductive structure with the multi-layer spacer therebetween; forming an air gap by removing the non-conformal sacrificial spacer; forming a capping layer covering the second conductive structure and the air gap; forming an opening that exposes a top surface of the second conductive structure by etching the capping layer; and forming a conductive pad coupled to the second conductive structure in the opening.

A method of forming a semiconductor structure includes following steps. A first isolation is formed between a pair of active regions. A gate structure is formed on the first isolation structure. The active regions are etched to form recesses with curved top surfaces. The active regions are etched again to change each of the curved top surfaces to be a top surface and a sidewall substantially perpendicular to the top surface. A pair of contacts is formed respectively on the active regions, such that each of the contacts has a bottom surface and a sidewall substantially perpendicular to the bottom surface.

The present invention relates to the field of semiconductor manufacturing technologies, in particular to a semiconductor device and a method of forming the same. The method of forming the semiconductor device includes the following steps: forming a substrate with a trench, a gate dielectric layer covering an inner wall of the trench, a barrier layer covering a portion of a surface of the gate dielectric layer, and a first gate layer filled on an surface of the barrier layer being disposed in the trench; removing a portion of the barrier layer to form an groove located between the first gate layer and the gate dielectric layer; forming a channel dielectric layer at least covering an inner wall of the groove and a top surface of the first gate layer; and forming a second gate layer at least partially filling an interior of the groove.

Provided is a semiconductor memory device comprising a device isolation pattern in a substrate and defining first and second active sections spaced apart from each other, wherein a center of the first active section is adjacent to an end of the second active section, a bit line that crosses over the center of the first active section, a bit-line contact between the bit line and the first active section, and a first storage node pad on the end of the second active section. The first storage node pad includes a first pad sidewall and a second pad sidewall. The first pad sidewall is adjacent to the bit-line contact. The second pad sidewall is opposite to the first pad sidewall. When viewed in plan, the second pad sidewall is convex in a direction away from the bit-line contact.

Embodiments of the present application provide a method of fabricating a memory, the method comprises: providing a substrate, wherein grooves are disposed in the substrate; forming a gate insulation layer on a surface of each groove; forming a metal layer on the gate insulation layer, the metal layer being at least fully filled in the groove; surface-processing the metal layer, to enhance flatness of a surface of the metal layer; and etching to remove the metal layer by a certain thickness to form a gate electrode whose top is lower than a surface of the substrate. Embodiments of the present application facilitate to solve the problem of unevenness at the top surface of the gate electrode.