The present disclosure relates to a semiconductor device and a forming method thereof. The forming method includes: providing a substrate; forming node contacts inside the substrate; forming landing pads on an upper surface of the substrate, where the landing pad is in contact with the node contact; forming a barrier layer on exposed surfaces of the landing pads and the node contacts; and after performing an electrical test on the semiconductor device on which the barrier layer is formed, removing the barrier layer on an upper surface of the landing pads.

The present disclosure provides a method for manufacturing a memory, including: providing a substrate, and forming a sacrificial layer on the substrate; patterning the sacrificial layer, and forming a plurality of discrete pseudo bit line layers on the substrate; forming a support layer, the support layer filling areas between the adjacent pseudo bit line layers; removing the pseudo bit line layers to form bit line spaces between adjacent parts of the support layer; forming bit line structures, the bit line structures filling the bit line spaces, and the bit line structures including a bit line conductive layer and a bit line insulating layer sequentially stacked; and removing the support layer, and forming openings between the adjacent bit line structures.

Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate and a plurality of discrete bit line structures disposed on the substrate, a conductive plug being arranged between each adjacent bit line structures, a top surface of the conductive plug being lower than or flush with top surfaces of the bit line structures; and landing pads, one of the landing pads covering at least the top surface and part of side wall surfaces of the conductive plug.

The present disclosure provides a semiconductor device and a manufacturing method thereof. The method for manufacturing a semiconductor device includes: providing a semiconductor substrate, with a plurality of trench isolation structures and a plurality of functional regions between the trench isolation structures being formed; forming a buried bit line structure, the buried bit line structure being formed in the semiconductor substrate; and forming a word line structure and a plurality of active regions, the word line structures and the active regions being formed on a surface of the semiconductor substrate and located above the functional regions.

The present application provides a memory and a manufacturing method thereof, and relates to the field of semiconductor technologies. The memory includes a substrate, the substrate is provided with a control region, and two sides of the control region are respectively provided with storage regions; each of the storage regions includes multiple rows of first active regions, and all the first contact regions in each row of the first active regions are connected by a bit line; the control region includes multiple second active regions, each of the second active regions is provided with a first gate and a first source/drain region and a second source/drain region that are located on two sides of the first gate, and all the first gates in the control region are connected with each other to form a control line; the first source/drain region and the second source/drain region in a same second active region are respectively connected with a corresponding bit line. The memory in the present application controls, through control lines, whether the bit line connected with the first source/drain region and the bit line connected with the second source/drain region are connected, so as to control the time of each read operation and write operation. In this way, the storage speed of the memory is increased and the performance of the memory is improved.

Provided are a semiconductor structure and method for preparing same. The semiconductor structure includes a gate, a source or a drain being provided in the substrate at either side of the gate; a dielectric layer; a contact structure; a first electrical connection part and a second electrical connection part arranged at intervals. The second electrical connection part is in contact with a partial top surface of the contact structure. The first electrical connection part includes a first barrier layer and a first conductive layer which are stacked. In a direction from the source to the drain, a distance between the sidewall of the first barrier layer facing the contact structure and the contact structure is a first distance, and a distance between the sidewall of the first conductive layer facing the contact structure and the contact structure is a second distance, the first distance being greater than the second distance.

A memory device and a forming method thereof are provided. The memory device includes: a semiconductor substrate, wherein multiple active regions are formed in the semiconductor substrate, and the multiple active regions are separated by multiple first trenches extending along a first direction and multiple second trenches extending along a second direction; a third trench, extending along the first direction and located in the semiconductor substrate at the bottom of the first trench; a bit line doped region, located in the semiconductor substrate on two sides of the third trench; a gate dielectric layer, located on a sidewall surface of the first trench and a sidewall surface of the second trench; a first dielectric layer that fills the third trench; a metal gate, located in the second trench and the first trench on the first dielectric layer.

The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method includes: providing a base and forming, on the base, a bit line contact region provided with a first groove; forming a first bit line contact layer in the first groove, wherein the first bit line contact layer in the first groove defines a second groove; forming a diffusion layer in the second groove, wherein the diffusion layer in the second groove defines a third groove; forming, in the third groove, a second bit line contact layer provided with a gap; and processing the diffusion layer.

The present disclosure provides a method for preparing a semiconductor memory device with air gaps between conductive features. The method includes forming an isolation layer defining a first active region in a substrate; forming a first doped region in the first active region; forming a first word line buried in a first trench adjacent to the first doped region; and forming a high-level bit line contact positioned on the first doped region; forming a first air gap surrounding the high-level bit line contact. The forming of the first word line comprises: forming a lower electrode structure and an upper electrode structure on the lower electrode structure. The forming of the upper electrode structure comprises: forming a source layer substantially covering a sidewall of the first trench; forming a conductive layer on the source layer; and forming a work-function adjustment layer disposed between the source layer and the conductive layer.

The present disclosure relates to a fabricating method of a semiconductor memory device including the following steps. Firstly, a substrate is provided, and a plurality of gate structures is formed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. Next, a plurality of isolation fins is formed on the substrate, wherein each of the isolation fins is parallel with each other and extends along the first direction, over each of the gate structures respectively. After forming the isolation fins, at least one bit line is formed on the substrate, extending along a second direction being perpendicular to the first direction, wherein the at least one bit line comprises a plurality of pins extending along a direction being perpendicular to the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.