The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; an isolation structure, formed in the substrate; a word line (WL), a part of the WL being located in the isolation structure; and a conductive portion, located at a bottom of the isolation structure.

A semiconductor memory device includes active sections that include first and second impurity regions and are defined by a device isolation layer. Word lines extend in a first direction on the active sections. Intermediate dielectric patterns cover top surfaces of the word lines. Bit-line structures extend on the word lines in a second direction intersecting the first direction. Contact plugs are disposed between the bit-line structures and are connected to the second impurity regions. Data storage elements are disposed on the contact plugs. The intermediate dielectric pattern includes a capping part that covers the top surfaces of the word lines and is buried in the substrate. Fence parts extend between the bit-line structures from the capping part.

Disclosed is a semiconductor device comprising a peripheral word line disposed on a substrate, a lower dielectric pattern covering the peripheral word line and including a first part that covers a lateral surface of the peripheral word line and a second part that covers a top surface of the peripheral word line, a contact plug on one side of the peripheral word line and penetrating the first and second parts, and a filling pattern in contact with the second part of the lower dielectric pattern and penetrating at least a portion of the second part. The contact plug includes a contact pad disposed on a top surface of the lower dielectric pattern, and a through plug penetrating the first and second parts. The filling pattern surrounds a lateral surface of the contact pad. The first and second parts include the same material.

An apparatus includes a substrate, a memory cell region provided over the substrate, a peripheral region provided over the substrate and adjacent to the memory cell region, and first, second, third, fourth and fifth word-lines each extending in parallel across the memory cell region and the peripheral region in numerical order. An offcut of the second word-line is interposed between edge portions of the first and third word-lines, and no offcut of the fourth word-line is interposed between edge portions of the third and fifth word-lines.

A memory device architecture, and method of fabricating a three dimensional device are provided. The memory device architecture may include a plurality of memory blocks, arranged in an array, wherein a given memory block comprises: a cell region, the cell region comprising a three-dimensional array of memory cells, arranged in a plurality of n memory cell layers; and a staircase region, the staircase region being disposed adjacent to at least a first side of the cell region, the staircase region comprising a signal line assembly that is coupled to the three-dimensional array of memory cells.

A semiconductor device and a method of fabricating the same are provided. According to the present invention, a semiconductor device comprises an active region formed in a substrate, and including flat surfaces and hole-shaped recess portions; upper-level plugs disposed over the flat surfaces; a spacer disposed between the upper-level plugs and providing a trench exposing the hole-shaped recess portions; a lower-level plug filling the hole-shaped recess portions; and a buried conductive line disposed over the lower-level plug and partially filling the trench.

A semiconductor device and a method for fabricating the same is provided. The semiconductor device includes a lower semiconductor film, a buried insulating film, and an upper semiconductor film which are sequentially stacked; an element isolation film defining an active region inside the substrate and including a material having an etching selectivity with respect to silicon oxide; a first gate trench inside the upper semiconductor film; a first gate electrode filing a part of the first gate trench; a second gate trench inside the element isolation film; and a second gate electrode filling a part of the second gate trench, a bottom side of the element isolation film being inside the lower semiconductor film.

Embodiments relate to a semiconductor structure and a method for fabricating the same. The method includes: providing a substrate; forming a first isolation trench in the substrate; filling a first isolation dielectric layer in the first isolation trench; forming a second isolation trench; forming a second isolation dielectric layer in the second isolation trench; forming word line structures arranged at intervals, where the word line structures extend along the second direction to wrap the channel regions of the active pillars in a same row; etching back the second isolation dielectric layer and the first isolation dielectric layer to expose second connection terminals of the active pillars; and forming a protective layer configured to define positions of the word line structures and wrap the second connection terminals of the active pillars.

A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

A method of forming a titanium nitride film on a substrate. The method includes: performing treatment of changing hydrophilicity of a base film formed on a substrate including a surface on which the base film capable of having its hydrophilicity changed is formed; and forming a titanium nitride film by vapor phase growth on a top surface of the base film subjected to the treatment of changing the hydrophilicity.