Some embodiments include an integrated assembly having an active region which contains semiconductor material. The active region includes first, second and third source/drain regions within the semiconductor material, includes a first channel region within the semiconductor material and between the first and second source/drain regions, and includes a second channel region within the semiconductor material and between the second and third source/drain regions. The semiconductor material includes at least one element selected from Group 13 of the periodic table. A digit line is electrically coupled with the second source/drain region. A first transistor gate is operatively proximate the first channel region. A second transistor gate is operatively proximate the second channel region. A first storage-element is electrically coupled with the first source/drain region. A second storage-element is electrically coupled with the third source/drain region. Some embodiments include methods of forming integrated assemblies.

The present disclosure provides a semiconductor structure having a fin structure. The semiconductor includes a substrate defined with an active region. A first gate structure is disposed in the active region and includes a dielectric material. A second gate structure is disposed in the active region and includes the dielectric material. A fin structure having a first top surface is arranged to alternate with the first gate structure and the second gate structure. The first gate structure has a second top surface and the second gate structure has a third top surface. The second top surface and the third top surface are lower than the first top surface.

Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.

The present disclosure relates to a semiconductor memory device and a method of fabricating the same, and the semiconductor memory device includes a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate and includes a first active region and a second active region. The first active region includes a plurality of active region units, and the second active region is disposed at an outer side of the first active region to directly connect to a portion of the active region units. The second active region includes a plurality of first openings disposed an edge of the second active region. The shallow trench isolation is disposed within the substrate, to surround the active structure.

A method for forming a semiconductor device includes the following operations. A stacked structure is provided, which includes a substrate, and sacrificial layers and semiconductor layers alternately stacked on surface of the substrate. Multiple first grooves and semiconductor pillars extending in first direction are included in the sacrificial layers and the semiconductor layers. Word line pillars are formed in second direction, intersect with the semiconductor pillars and surround the semiconductor pillars. Sources and drains are formed respectively on either side of the semiconductor pillars surrounded by the word line pillars by an epitaxial growth process. Bit lines are formed on a side of the sources or the drains, are connected with same, and extend in third direction. The first, second and third directions are pairwise perpendicular. Capacitors are formed on a side of the sources or the drains where the bit lines are not formed to form a semiconductor device.

Embodiments provide a method for fabricating a semiconductor structure and a structure thereof. The method includes: providing a substrate; forming, on the substrate, semiconductor channels arranged in an array along a first direction and a second direction; forming bit lines extending along the first direction, wherein the bit lines are positioned in the substrate, and each of the bit lines is electrically connected to the semiconductor channels arranged along the first direction; forming word lines extending along the second direction, wherein the word lines wrap part of side surfaces of the semiconductor channels arranged along the second direction, where one of the word lines includes two sub word lines arranged at intervals along the first direction, and the sub word lines cover part of opposite side surfaces of the semiconductor channels along the first direction; and forming isolation structures positioned between adjacent word lines and between adjacent sub word lines.

Embodiments relate to a semiconductor structure and a method for fabricating the same. The method includes: providing a substrate, a first trench being formed in the substrate; forming a protective layer in the first trench, the protective layer covering a side wall and a bottom of the first trench; etching the protective layer and the substrate at the bottom of the first trench to form second trenches; forming a passivation layer at a bottom of each of the second trenches; and etching a side wall of each of the second trenches to form a groove, and forming a dielectric layer in the groove. The method can eliminate a process of forming a bit line contact structure, thereby reducing resistance of a bit line and simplifying fabrication processes of the bit line.

Embodiments provide a semiconductor structure and a method thereof. The method includes: providing a first substrate, and forming a drive pad on the first substrate; providing a second substrate, and forming active pillars and a bit line in sequence on a side of the second substrate, wherein a side of the bit line is connected to the active pillars, and a surface of the bit line facing away from the active pillars is exposed on a surface of the second substrate; bonding the bit line to the drive pad correspondingly; thinning the second substrate from a side of the second substrate facing away from the first substrate until the active pillars are exposed; and forming a storage capacitor on sides of the active pillars facing away from the drive pad, the storage capacitor being connected to the active pillars.

Embodiments provide a semiconductor structure and a formation method thereof. The semiconductor structure includes: a substrate provided with semiconductor pillars arranged at intervals, the semiconductor pillars including a first doped region, a channel region and a second doped region sequentially arranged along a direction distant from a surface of the substrate; and a plurality of word lines extending along a first direction and an insulating layer between adjacent word lines. Each word line surrounds the channel region of the semiconductor pillars arranged along the first direction, and along the direction distant from the surface of the substrate, a width of the insulating layer perpendicular to the first direction gradually decreases. The embodiments are at least advantageous to ensuring that the word lines have better continuity.

Embodiments relate to a semiconductor device and a forming method. The semiconductor device includes: a substrate; a memory array positioned on the substrate and at least including memory cells spaced along a first direction, each of the memory cells including a transistor, the transistor including a gate electrode, channel regions distributed on two opposite sides of the gate electrode along a third direction, and a source region and a drain region distributed on two opposite sides of each of the channel regions along a second direction, the first direction and the third direction being directions parallel to a top surface of the substrate, the first direction intersecting with the third direction, and the second direction being a direction perpendicular to the top surface of the substrate; and a word line extending along the first direction and continuously electrically connected to the gate electrodes spaced along the first direction.