A method for forming a semiconductor structure comprises: providing a substrate, which includes a first area and a second area arranged in sequence in a second direction, the first area including active layers arranged at intervals in a third direction; forming an initial gate structure located on a surface of each active layer in the first area; etching the initial gate structures to form comb-shaped gate structures stacked in a third direction, each comb-shaped gate structure including first gate structures arranged at intervals in the first direction; and forming bit line structures extending in the third direction and capacitor structures extending in the second direction in the second area, the bit line structures and the capacitor structures are connecting to the first gate structures.

A method for forming a semiconductor structure includes the following: a substrate is provided, the substrate including a first area and a second area arranged in sequence in a second direction and T-shaped active pillars located in the first area and the second area and arranged in an array in a first direction and a third direction, the first, second and third directions being perpendicular to one another, and the first and second directions being parallel to a surface of the substrate; T-shaped gate structures located on surfaces of the T-shaped active pillars and bit line structures extending in the third direction are formed in the first area, a plurality of T-shaped gate structures located in the first direction being interconnected; and capacitor structures extending in the second direction is formed in the second area, the bit line structures and the capacitor structures being connected to the T-shaped gate structures.

An embodiment provides a method for fabricating a semiconductor structure. The method includes: providing a semiconductor substrate having an active area, the active area including a first active area and a second active area isolated from each other; forming a bitline contact groove on the semiconductor substrate, the bitline contact groove exposing the first active area; forming an etch stop layer covering a sidewall of the bitline contact groove, the etch stop layer exposing a partial area of the first active area at a bottom of the bitline contact groove; etching the semiconductor substrate by using the etch stop layer as a mask to form a pit at the bottom of the bitline contact groove, the pit being at least partially positioned in the first active area; removing the etch stop layer; forming a bitline structure; and forming a conductive plug electrically connected to the second active area.

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate including a peripheral region, wherein the peripheral region includes a wire lead-out area, and the substrate is arranged with a plurality of discrete bit line structures; a dielectric layer formed between the adjacent bit line structures, wherein the peripheral region is arranged with a first contact hole; a wire lead-out area with a second through hole; a filling layer filling part of a first contact hole, wherein a remaining part of the first contact hole is defined as a first through hole; a first conductive layer located in the first through hole and the second through hole; and a conductive connecting wire located over the dielectric layer and being in contact with the first conductive layer in the wire lead-out area.

A semiconductor structure includes a substrate; at least one layer of memory structure formed on the substrate, in which each layer of memory structure comprises a bit line structure and a plurality of capacitor structures symmetrically distributed on both sides of the bit line structure, the plurality of capacitor structures and the bit line structure extend in a first direction parallel to the substrate surface; a plurality of word line structures formed in the at least one layer of memory structure, which pass through the at least one layer of memory structure and extend in a second direction perpendicular to the substrate surface.

The present application discloses a method for fabricating the semiconductor device. The method for fabricating a semiconductor device includes providing a substrate having a first lattice constant and forming a first word line positioned in the substrate and a plurality of stress regions positioned adjacent to lower portions of sidewalls of the first word line. The plurality of stress regions have a second lattice constant, the second lattice constant of the plurality of stress regions is different from the first lattice constant of the substrate.

A method for manufacturing a semiconductor structure includes the following operations. A substrate is provided, and is etched to form first isolation trenches in a cell region and a second isolation trench in a peripheral region. A first isolation dielectric layer is filled in each of the first isolation trenches and an isolation structure is formed in the second isolation trench. A patterned mask layer is formed on surfaces of the cell region and the peripheral region. The substrate and the first isolation dielectric layer are etched based on the patterned mask layer to form the third isolation trenches extending along a second direction. The third and first isolation trenches isolate multiple active pillars. The active pillar includes a first connecting end, a second connecting end and a channel region.

Disclosed are DRAM devices and methods of forming DRAM devices. One non-limiting method may include providing a device, the device including a plurality of angled structures formed from a substrate, a bitline and a dielectric between each of the plurality of angled structures, and a drain disposed along each of the plurality of angled structures. The method may further include providing a plurality of mask structures of a patterned masking layer over the plurality of angled structures, the plurality of mask structures being oriented perpendicular to the plurality of angled structures. The method may further include etching the device at a non-zero angle to form a plurality of pillar structures.

A semiconductor structure includes: a substrate; a plurality of active layers arranged on the substrate and spaced apart from each other; and a plurality of bit lines, spaced apart from each other in a first direction and extending in a second direction. A first portion of each bit line covers side surfaces of respective active layers of the plurality of active layers, and a second portion of each bit line is located in the respective active layers. The first direction and the second direction are parallel to a surface of the substrate, and the first direction intersects with the second direction.

Provide is a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor memory. The method includes the following operations. A substrate is provided. Multiple silicon pillars are formed in the substrate, and extend along a first direction. In the first direction, each of the silicon pillars includes a first portion and a second portion. An insulating layer is formed in the second portion of the silicon pillar. A conductive layer is formed in the first portion of the silicon pillar. A capacitor layer is formed on surfaces of the insulating layer and the conductive layer of the silicon pillar.