A one-time programmable (OTP) vertical field-effect transistor (VFET) can be fabricated on the top surface of an integrated circuit (IC) substrate having a fin. A doped layer can be deposited onto the top surface to create an OTP VFET drain. A dielectric layer can be formed onto side surfaces of the fin, and a gate dielectric layer formed onto side surfaces of the dielectric layer. A metal layer formed onto side surfaces of the gate dielectric layer can create an OTP VFET gate. An electrically insulative top spacer layer can then be attached to top edges of the dielectric, the gate dielectric layer, and the metal layer. A doped structure formed onto the top surface of the fin can create an OTP VFET source. A voltage applied to a portion of the gate dielectric layer can cause dielectric breakdown, which can be used to store a data value.

A semiconductor device includes a substrate having a first active region; first and second gate electrodes disposed on the first active region; first, second and third impurity regions disposed in the first active region; first, second and third active contacts disposed on and connected to the first, second and third impurity regions; a first power line electrically connected to the first impurity region through the first active contact; and a first bit line electrically connected to the second and third impurity regions through the second and third active contacts. The first gate electrode and the first and second impurity regions form a first transistor of a first memory cell. The second gate electrode and the second and third impurity regions form a second transistor of a second memory cell. The second impurity region is a drain of the first and second transistors of the first and second memory cells.

A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.

In some implementations, fluorine is oxidized after dry etching an oxide layer above a source/drain contact and before cleaning. Accordingly, less hydrofluoric acid is formed during cleaning, which reduces unexpected wet etching of the source/drain contact. This allows for forming a recess in the source/drain contact with a depth to width ratio in a range from approximately 1.0 to approximately 1.4 and prevents damage to a layer of silicide below the source/drain that can be caused by excessive hydrofluoric acid. Additionally, or alternatively, the recess is formed using multiple wet etch processes, and any residual fluorine is oxidized between the wet etch processes. Accordingly, each wet etching process may be shorter and less corrosive, which allows for greater control over dimensions of the recess. Additionally, less hydrofluoric acid may be formed during cleaning processes between the wet etch processes, which reduces the etching of the source/drain contact between processes.

A mask read only memory device is provided. Single-transistor memory cells are arranged in rows and columns. Each word line is associated with a corresponding row. Each bit line is associated with a corresponding column. Each first reference line selectively provides a first potential in a first phase and a second potential in a second phase. Each second reference line selectively provides the second potential in the first read phase and the first potential in the second phase. Each memory cell has a gate coupled to a word line, a drain coupled to a bit line and a source terminal either floating, grounded or coupled to one among a first reference line and a second reference line. One of first to fourth logic values is read during a read operation of the memory cell.

A semiconductor device includes a programmable memory array comprising plural memory units disposed above a substrate. One of the memory units comprises a gate electrode disposed above the substrate, a conductive portion spaced apart from the gate electrode, and a dielectric layer contacting the conductive portion and separated from the gate electrode, and the dielectric layer defining a threshold voltage of the related memory unit, wherein at least two of the memory units have different threshold voltages.

Various implementations described herein are related to a device including a bitcell having a bitcell layout with a first metal layer, a second metal layer and a via programming layer. The device may have a via marking layer provided in the bitcell layout for the bitcell, and the via marking layer controls optical proximity correction of the first metal layer and the second metal layer.

A read-only memory (ROM) device includes a complementary field effect transistor (CFET) device which has a first semiconductor device of a first type, and a second semiconductor device of a second type different from the first type. The second semiconductor device is over or under the first semiconductor device. A first word line is electrically coupled to a gate of the first semiconductor device. A second word line is electrically coupled to a gate of the second semiconductor device. At least one bit line is electrically coupled to at least one of a first source/drain of the first semiconductor device, or a first source/drain of the second semiconductor device.

An integrated circuit includes a read only memory (ROM) cell which includes an on-cell. The on-cell includes: a first source/drain region and a second source/drain region; a frontside contact between the first source/drain region and a bit line on a front side of the on-cell; and a backside contact between the second source/drain region and a power line on a back side of the on-cell. The bit line is configured to provide a bit line signal to the on-cell, and the power line is configured to provide a power supply voltage signal to the on-cell. The bit line and the power line are vertically aligned with each other.

Described herein is a ROM architecture featuring a ROM bitcell without a transistor, a ROM architecture wherein the bitcell device gate goes to a column address and the local bitline is sensed per row per mux, a ROM architecture wherein the bitcell device gate goes to the column address and the full row of bitcells is enabled by a row enable signal, and a ROM architecture wherein the bitcell device gate goes to the row address and the full column of bitcells is enabled by a column enable signal. The presently described architectures provide large advantages in terms of PPA.