A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.

A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.

A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.

A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.

A 3D semiconductor memory device includes a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure comprising stacked electrodes, and a vertical channel structure penetrating the electrode structure. The peripheral circuit structure includes a dummy interconnection structure under the second substrate. The dummy interconnection structure includes stacked interconnection lines, and a via connecting a top surface of an uppermost one of the interconnection lines to a bottom surface of the second substrate.

A 3D semiconductor memory device includes a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure comprising stacked electrodes, and a vertical channel structure penetrating the electrode structure. The peripheral circuit structure includes a dummy interconnection structure under the second substrate. The dummy interconnection structure includes stacked interconnection lines, and a via connecting a top surface of an uppermost one of the interconnection lines to a bottom surface of the second substrate.

In some implementations, one or more semiconductor processing tools may form a triple-stacked polysilicon structure on a substrate of a semiconductor device. The one or more semiconductor processing tools may form one or more polysilicon-based devices on the substrate of the semiconductor device, wherein the triple-stacked polysilicon structure has a first height that is greater than one or more second heights of the one or more polysilicon-based devices. The one or more semiconductor processing tools may perform a chemical-mechanical polishing (CMP) operation on the semiconductor device, wherein performing the CMP operation comprises using the triple-stacked polysilicon structure as a stop layer for the CMP operation.

A flash memory is provided and includes a substrate including a memory cell region; a memory transistor array including memory transistors and selecting transistors in the memory cell region; a functional layer covering outer surfaces of the memory transistors and selecting transistors, as well as surfaces of the substrate between adjacent memory transistors and selecting transistors; a dielectric layer covering top surfaces of the memory transistors and selecting transistors and fills gaps between each selecting transistor and a corresponding adjacent memory transistor; and air gaps formed between adjacent memory transistors. Each selecting transistor is used for selecting one column of memory transistors in the memory transistor array. The functional layer has a roughened surface capable of absorbing water. The air gaps in the flash memory are water vapor induced air gaps.

An integrated circuit device includes a semiconductor substrate having a memory area and a logic area. A memory cell in the memory area includes a select gate separated from a floating gate by a floating gate spacer. A select gate spacer is formed on a side of the select gate opposite the floating gate. The select gate spacer has a uniform thickness over most of the select gate. The first layer of the select gate spacer may be formed by oxidizing the select gate electrode. A second layer of the select gate spacer may be formed by atomic layer deposition. The memory area may be covered by a protective layer while spacers are formed adjacent logic gates in the logic region.