A semiconductor device includes a horizontal wiring layer on a substrate, a stack structure disposed on the horizontal wiring layer and including insulating layers and electrode layers alternately stacked on each other, and a pillar structure extending into the horizontal wiring layer and extending through the stack structure. The electrode layers include one or a plurality of selection lines adjacent to an uppermost end of the stack structure, and word lines surrounding the stack structure below the one or plurality of selection lines. The pillar structure includes a variable resistive layer, a channel layer between the variable resistive layer and the stack structure, a gate dielectric layer between the channel layer and the stack structure, and a blocking pattern disposed between the variable resistive layer and the channel layer and being adjacent to a first selection line among the one or plurality of selection lines.

A vertical repetition of a unit layer stack includes an insulating layer, a first sacrificial material layer, another insulating layer, and a second sacrificial material layer. A memory opening is formed through the vertical repetition, and a memory opening fill structure is formed in the memory opening. A backside trench is formed through the alternating stack. The first sacrificial material layers are replaced with first electrically conductive layers, and the second sacrificial material layer are replaced with second electrically conductive layers after formation of the first electrically conductive layers.

Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Two word line plates in a same plane may be activated via a shared electrode. Memory cells coupled with the two word line plates sharing the electrode, or a subset thereof, may represent a logical page for accessing memory cells. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.

Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.

A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; and a via disposed through the first level, where the first level thickness is less than two microns.

A RRAM and its manufacturing method are provided. The RRAM includes an interlayer dielectric layer, a first bottom contact structure, and a second bottom contact structure formed on a substrate. A first memory cell is formed on the first bottom contact structure. The first memory cell includes a first bottom electrode layer which includes a first conductive region. A pattern in which the first conductive region is vertically projected on the first bottom contact structure is a first projection pattern. A second memory cell is formed on the second bottom contact structure. The second memory cell includes a second bottom electrode layer which includes a second conductive region. A pattern in which the second conductive region is vertically projected on the second bottom contact structure is a second projection pattern. The second projection pattern is different from the first projection pattern.

A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, wherein the insulating patterns protrude farther towards the channel structure than a sidewall of the hard mask pattern, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns.

A memristive device is described. The memristive device includes a first layer having a first plurality of conductive lines, a second layer having a second plurality of conductive lines, and memristive interlayer connectors. The first and second layers differ. The first and second pluralities of conductive lines are each lithographically defined. The first and second pluralities of conductive lines are insulated from each other. The memristive interlayer connectors are memristively coupled with a first portion of the first plurality of conductive lines and memristively coupled with a second portion of the second plurality of conductive lines. The memristive interlayer connectors are thus sparsely coupled with the first and second pluralities of conductive lines. Each memristive interlayer connector includes a conductive portion and a memristive portion. The memristive portion is between the conductive portion and corresponding line(s) of the first plurality of conductive lines and/or the second plurality of conductive lines.

A 3D semiconductor device including: a first level including a single crystal silicon layer and a plurality of first transistors each including a single crystal channel; a first metal layer overlaying the plurality of first transistors; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a second level, where the second level overlays the first level and includes a plurality of second transistors; a fourth metal layer overlaying the second level; and a connective path between the fourth metal layer and either the third metal layer or the second metal layer, where the connective path includes a via disposed through the second level and has a diameter of less than 500 nm and greater than 5 nm, where the third metal layer is connected to provide a power or ground signal to at least one of the second transistors.

Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.